GaN Depletion-Mode Amplifier Bias Circuit for Low-Voltage CMOS Control
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Solution Overview
Problem
Providing a low voltage CMOS bias control circuit for high voltage GaN transistors is challenging due to the significant voltage difference between sub-micron Si CMOS circuits and GaN transistors, which operate in tens to hundreds of volts.
Innovation Solution
A circuit using a current diversion process with a control circuit that selectively enables or inhibits current to the biasing circuitry, allowing for control of the bias voltage at the gate electrode of the transistor, implemented with depletion mode transistors and diodes, enabling control with submicron Si CMOS operated at less than 2.5V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a gate switch is used to control the depletion mode transistor, then switching speed is improved, but the control circuit requires high voltage supplies that are incompatible with low voltage CMOS technology
Solution Approach 1:
The patent introduces a bias circuit as an intermediary between the low voltage CMOS control circuit and the high voltage depletion mode transistor. This bias circuit generates the necessary high voltage gate control signals from low voltage CMOS outputs, enabling the CMOS circuit to control the power transistor without direct high voltage exposure. The bias circuit acts as a voltage level translator and mediator, resolving the incompatibility between low voltage control logic and high voltage power switching.
2Reliability
If high voltage supplies are used for GaN transistor control, then proper bias control is achieved, but integration with low voltage Si CMOS circuits becomes difficult
Solution Approach 1:
The patent segments the control system into two distinct voltage domains: a low voltage domain for CMOS control circuits and a high voltage domain for GaN power transistor operation. The bias circuit serves as the interface between these segmented domains, allowing each to operate at its optimal voltage level independently. This segmentation enables monolithic integration by preventing high voltage stress from affecting the delicate CMOS circuits while still providing accurate high voltage bias control to the GaN device.
3Device complexity
If direct current control is used from CMOS to GaN, then circuit simplicity is maintained, but voltage level mismatch prevents proper operation
Solution Approach 1:
The bias circuit serves as a voltage level mediator that translates low voltage CMOS control signals into appropriate high voltage levels for GaN transistor gate control. This intermediary approach maintains circuit simplicity by using a straightforward voltage translation architecture rather than complex level-shifting networks, while ensuring proper voltage level compatibility between the dissimilar technology nodes.
Data Source
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AI summary
A circuit (10) having an amplifier (11), comprising: a depletion mode transistor (Q1) having a source electrode coupled to a reference potential; a drain electrode coupled to a potential (VDD) more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit (10) includes a bias circuit (12), comprising: a current source; and biasing circuitry coupled to the current source and between the potential (VDD) more positive than the reference potential and a potential (-Vss) more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.