GaN Bonding Pad Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Current gallium nitride-based semiconductor devices face challenges in reducing parasitic capacitance, which affects their input and output capacitance requirements, and this is complicated by the need to minimize the area of the field plate and increase the thickness of the medium between the field plate and the 2DEG, leading to reduced withstand voltage and increased production complexity.
Innovation Solution
The semiconductor device incorporates an epitaxial structure with a two-dimensional electron gas, an electrode structure, and dielectric layers to form an electrical connection between the electrode structure and bonding pad, with the bonding pad partially located in the active region, shielding parasitic capacitance and allowing for flexible arrangement, thus reducing overall device area and improving integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of the field plate is minimized and the thickness of the medium between the field plate and the 2DEG is increased to reduce parasitic capacitance, then the input and output capacitance requirements are improved, but the withstand voltage is reduced and production complexity is increased
Solution Approach 1:
The patent moves the bonding pad from the conventional position outside the active region to a position partially within the active region, utilizing the vertical dimension and spatial rearrangement to reduce parasitic capacitance without increasing production complexity
Solution Approach 2:
The patent introduces an electrode connection line as an intermediary element that connects the electrode structure to the bonding pad through dielectric layers, enabling flexible arrangement and effective parasitic capacitance shielding while maintaining manageable production complexity
2Ease of manufacture
If the bonding pad is located outside the active region, then the device structure is conventional and easy to manufacture, but the parasitic capacitance is not effectively shielded and the device area is larger
Solution Approach 1:
The patent relocates the bonding pad to the active region and uses the electrode connection line traversing through dielectric layers to establish connection, utilizing spatial dimensionality change to achieve both effective parasitic capacitance shielding and acceptable manufacturing ease
Solution Approach 2:
The electrode connection line acts as an intermediary that enables the bonding pad to be positioned within the active region while maintaining electrical connection, effectively shielding parasitic capacitance without significantly complicating the manufacturing process
3Reliability
If the electrode connection line is arranged to reduce parasitic capacitance, then the capacitance requirements are met, but the device area increases and integration is reduced
Solution Approach 1:
The patent applies local quality by positioning the bonding pad partially within the active region and using dielectric layers with specific properties in critical areas to shield parasitic capacitance locally, meeting capacitance requirements without significantly increasing overall device area
Solution Approach 2:
The patent utilizes vertical stacking of dielectric layers and horizontal arrangement of connection lines to achieve effective parasitic capacitance reduction through spatial optimization, meeting capacitance requirements while maintaining compact device area through three-dimensional space utilization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, meets high capacitance requirements, and facilitates miniaturization and cost reduction by shielding capacitance with the two-dimensional electron gas and optimizing the electrode connection, leading to improved performance and design efficiency.
Implementation Method 1
at least a part of the ohmic contact electrode bonding pad is located in the active region... shielding parasitic capacitance
Data Source
AI summary
A semiconductor device includes an active region; a substrate; an epitaxial structure; an electrode structure, and the electrode structure including a plurality of ohmic contact electrodes; a first dielectric layer; an electrode connection line, the electrode connection line including an ohmic contact electrode connection line, and the ohmic contact electrode connection line being electrically connected to the ohmic contact electrode; an second dielectric layer; an electrode bonding pad, the electrode bonding pad including an ohmic contact electrode bonding pad, the ohmic contact electrode bonding pad being electrically connected to the ohmic contact electrode connection line, and at least a part of the ohmic contact electrode bonding pad being located in the active region, reducing a parasitic capacitance between the ohmic contact electrode bonding pad and the substrate, and further satisfying high requirements on an input capacitance and an output capacitance of the semiconductor device.