GaN Buffer Layer Bending Threading Dislocations

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Solution Overview

Problem

GaN-based compound semiconductor electronic devices face challenges in achieving low on-resistance due to high dislocation density caused by strain between the substrate and epitaxial layer, leading to crystallinity issues and warp in the epitaxial substrate.

Innovation Solution

A semiconductor electronic device structure incorporating a buffer layer with alternating nitride-based compound semiconductor layers and a dislocation reducing layer with an uneven boundary surface, which reduces threading dislocation density by bending and eliminating dislocations, thereby improving crystallinity and reducing warp.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If GaN layer is directly grown epitaxially on Si substrate, then manufacturing process is simplified, but tensile strain develops causing concave warp and crystallinity deterioration

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidcrystallinity quality

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

A buffer layer comprising alternating GaN and AlN layers is introduced between the Si substrate and the GaN-based compound semiconductor layer. This intermediary buffer layer accommodates the lattice mismatch and thermal expansion differences, preventing tensile strain accumulation that would otherwise cause concave warp and crystallinity deterioration, while still allowing for a feasible manufacturing process

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If buffer layer with composite lamination of GaN and AlN layers is used, then crystallinity is improved and warp is reduced, but threading dislocations extend to semiconductor operation layer

Engineering Contradiction:

Improvecrystallinity qualityVSAvoiddislocation density in operation layer

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

An inclined interface is formed between the buffer layer and the GaN-based compound semiconductor layer instead of a flat interface. This curved/angled boundary causes threading dislocations to bend and terminate at the inclined interface, preventing them from extending into the semiconductor operation layer, thereby improving device reliability while maintaining the crystallinity benefits of the composite buffer layer

Inventive Principle:

Principle #14Spheroidality (Curvature)

3Reliability

If dislocation density is decreased in semiconductor operation layer, then on-resistance decreases, but requires additional layer structure increasing device complexity

Engineering Contradiction:

Improveon-resistanceVSAvoidlayer structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The buffer layer serves multiple functions simultaneously: it acts as a strain-relieving layer to prevent warp and maintain crystallinity, and as a dislocation-blocking layer through its inclined interface to reduce threading dislocations in the operation layer. This merging of functions reduces the need for additional separate layers, thereby limiting the increase in device complexity while achieving lower on-resistance

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively decreases on-resistance and warp in GaN-based field effect transistors, enhancing their performance and reliability by reducing dislocation density and strain in the semiconductor operating layer.

Implementation Method 1

threading dislocation extending from the lower layer area to the upper layer area is bent at the boundary surface

Methodology Applied

Scientific EffectDislocation bending:

Implementation Method 2

a buffer surface is usually arranged between the Si substrate and GaN layer as a strain-relieving layer

Methodology Applied

Scientific EffectStrain relief: Stress Relaxation

Implementation Method 3

there is a considerable difference in the lattice constant and coefficient of thermal expansion of Si and GaN

Methodology Applied

Scientific EffectLattice matching:

Implementation Method 4

there is a considerable difference in the lattice constant and coefficient of thermal expansion of Si and GaN

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS8338859B2Semiconductor electronic device having reduced threading dislocation and method of manufacturing the same

Publication Date: 2012.12.25 FURUKAWA ELECTRIC CO LTD

AI summary

A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area to the upper layer area is bent at said boundary surface.