Four-Phase GaN Buffer Circuit for Rail-to-Rail Gate Driving
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Solution Overview
Problem
Current monolithic GaN integrated circuits lack complementary p-channel transistors, leading to increased static power consumption and inefficiency in implementing high-speed logic circuits and complex digital functions, with existing gate drivers suffering from limitations such as rail-to-rail driving issues, voltage drops, and complex bootstrap stages.
Innovation Solution
A fully integrated GaN driver circuit is developed, featuring a buffer circuit with a push-pull stage and pre-buffer stages that drive GaN power switches in four phases, enabling rail-to-rail driving and reducing power consumption, implemented in a monolithic GaN technology on the same substrate as the power transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If monolithic GaN integrated circuits are used, then integration density and switching frequency are improved, but static power consumption increases due to lack of complementary p-channel transistors
Solution Approach 1:
The buffer circuit is divided into multiple operational phases (first phase through fourth phase) with different transistor configurations active in each phase. This segmentation allows the circuit to achieve rail-to-rail driving capability while minimizing static power consumption by ensuring that not all transistors are conductive simultaneously, thus resolving the contradiction between high switching frequency and low static power consumption in monolithic GaN integration.
2Adaptability or versatility
If conventional Si-based gate drivers are used, then design flexibility is maintained, but parasitic inductance and electromagnetic emissions increase
Solution Approach 1:
The gate driver circuit and GaN power switches are merged into a single monolithic GaN integrated circuit, eliminating separate Si-based driver components. This integration reduces parasitic inductance in the gate loop and minimizes electromagnetic emissions while maintaining design flexibility through the modular buffer circuit architecture with controllable transistor phases, thereby resolving the contradiction between design flexibility and parasitic reduction.
3Reliability
If rail-to-rail driving is implemented, then power switch performance is improved, but circuit complexity increases
Solution Approach 1:
The buffer circuit employs periodic action by operating in distinct phases (first phase through fourth phase) where different transistor combinations are activated sequentially. This phased operation achieves rail-to-rail driving capability for improved power switch performance while managing circuit complexity through systematic phase control rather than requiring all transistors to be simultaneously active, thus resolving the contradiction between reliability and device complexity.
Data Source
AI summary
A buffer circuit for driving a GaN power switch includes an input node to receive an input signal and an output node to produce a gate signal for the GaN power switch. The buffer includes a push-pull stage that includes a first transistor coupled between a supply voltage node and the output node, a second transistor coupled between the supply voltage node and the output node, a third transistor coupled between the output node and a reference voltage node, and a fourth transistor coupled between the output node and the reference voltage node. The buffer includes a pre-buffer stage configured to receive the input signal and to produce respective driving signals for the first, second, third and fourth transistors to produce the gate signal at the output node in four consecutive phases.