GaN Semiconductor Buffer Layer Resistivity Control
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Solution Overview
Problem
GaN semiconductor devices face a significant issue known as 'drain lag' due to trapping phenomena caused by lattice mismatches and dislocations, leading to undesirable leakage current and output conductance, which affects their performance.
Innovation Solution
Incorporating an enhanced resistivity region below the device channel within the buffer and nucleation layers through ion implantation, which disrupts the lattice and reduces leakage current without significantly increasing drain lag, by making these layers more electrically inert.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the nucleation and buffer layers are made electrically inactive to reduce leakage current, then leakage current is reduced, but drain lag increases due to trapping phenomena in the epitaxial material
Solution Approach 1:
The patent applies local quality by creating a high-resistivity region specifically in the buffer layer through ion implantation, while keeping the channel layer and other regions unaffected. This localized modification reduces leakage current through the buffer layer without significantly impacting the channel performance, thereby resolving the contradiction between reducing leakage current and maintaining low drain lag.
Solution Approach 2:
The patent changes the electrical parameter (resistivity) of the buffer layer by introducing ions through ion implantation. This transforms the buffer layer from a low-resistivity state to a high-resistivity state, making it more electrically inactive and reducing leakage current while maintaining acceptable drain lag characteristics.
2Object-generated harmful factors
If iron or carbon are incorporated as active dopants in the nucleation layer to reduce leakage current, then leakage current is reduced, but drain lag increases significantly
Solution Approach 1:
The patent uses ion implantation as an intermediary process to introduce compensating dopants into the buffer layer. This intermediary approach allows for controlled modification of the buffer layer's electrical properties without directly incorporating harmful dopants like iron or carbon into the nucleation layer, thus reducing leakage current while avoiding significant drain lag increase.
Solution Approach 2:
The patent employs compensating dopants that are introduced temporarily through ion implantation to create a high-resistivity region. These dopants serve their purpose of reducing leakage current and can be managed without the long-term harmful effects of incorporating iron or carbon as permanent substitutional impurities in the nucleation layer.
3Object-generated harmful factors
If the epitaxial material between the channel and base substrate is made more resistive, then leakage current is reduced, but the crystal lattice is disrupted increasing drain lag
Solution Approach 1:
The patent changes the resistivity parameter of the buffer layer through controlled ion implantation. By carefully selecting ion species, energy, and dose, the buffer layer is transformed into a high-resistivity region that reduces leakage current while the crystal lattice disruption is minimized and confined to the buffer layer, not affecting the channel layer significantly.
Solution Approach 2:
The patent applies local quality by confining the ion implantation effects to the buffer layer region. The high-resistivity region is created locally in the buffer layer through ion implantation, while the channel layer maintains its original quality and low drain lag characteristics, thus resolving the contradiction between reducing leakage current and maintaining channel performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a substantial reduction in leakage current while maintaining low drain lag, thereby improving the overall performance of GaN semiconductor devices.
Implementation Method 1
an ion implantation process is performed to implant ions into and through at least a portion of the buffer layer, and also through the underlying nucleation layer
Data Source
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AI summary
Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base substrate, a first semiconductor layer disposed over the nucleation layer, a second semiconductor layer disposed over the first semiconductor layer, a channel within the second semiconductor layer and proximate to an upper surface of the second semiconductor layer, and an enhanced resistivity region with an upper boundary proximate to an upper surface of the first semiconductor layer. The enhanced resistivity region has an upper boundary located a distance below the channel. Embodiments of a method of fabricating the semiconductor device include implanting one or more ion species through the first semiconductor layer to form the enhanced resistivity region.