Multi-Layer Group III-Nitride Buffer Segmentation for Wafer Bowing
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Solution Overview
Problem
The challenge lies in forming thick, high-quality gallium nitride epitaxial layers over large silicon substrates, which are hindered by thermal expansion coefficient mismatches and wafer bowing, leading to tensile stress, cracking, and reduced breakdown voltage in devices like FETs and HEMTs, limiting cost reductions and manufacturability.
Innovation Solution
A multi-layer Group III-nitride buffer structure is formed by creating isolated epitaxial regions and using dielectric layers to relieve stress, allowing for thicker buffer layers without cracking, achieved through techniques like MOCVD and MBE, enabling higher breakdown voltages and cost-effective production on larger substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thick gallium nitride epitaxial layers are formed over large silicon substrates, then breakdown voltage of devices is improved, but thermal expansion mismatch causes tensile stress leading to wafer bowing and cracking
Solution Approach 1:
The buffer layer is divided into multiple discrete islands separated by dielectric material rather than forming a continuous layer. This segmentation allows each island to independently accommodate thermal stress without transmitting it across the entire wafer, preventing cracking while maintaining sufficient thickness for high breakdown voltage devices
Solution Approach 2:
A dielectric material is introduced as an intermediary substance between the gallium nitride buffer islands and the silicon substrate. This dielectric layer acts as a stress buffer that decouples the thermal expansion mismatch between the GaN and Si, allowing the GaN islands to contract freely during cooling without inducing tensile stress that would cause cracking
2Strength
If continuous gallium nitride buffer layers are formed to achieve high breakdown voltage, then device performance is improved, but wafer bowing occurs due to thermal contraction mismatch
Solution Approach 1:
The continuous buffer layer is segmented into discrete islands, which eliminates the cumulative thermal stress that causes wafer bowing. Each isolated island can contract independently during cooling without affecting the overall wafer flatness, while still providing sufficient thickness for high-voltage device operation
3Productivity
If larger silicon substrates are used for production, then manufacturing cost per circuit is reduced, but epitaxial layer cracking increases due to thermal stress
Solution Approach 1:
The buffer layer is segmented into islands that can be formed across large substrate areas without inducing cracking. This allows the use of six-inch and larger silicon wafers for production while maintaining high yield, as the segmented structure prevents the propagation of thermal stress across the entire large substrate
Solution Approach 2:
The dielectric material serves as a stress-relieving intermediary that enables the formation of thick GaN buffer layers on large substrates. By isolating the GaN regions and providing a compliant interface, the dielectric allows large-area production without the cracking that would otherwise limit substrate size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of thicker buffer layers that reduce wafer bowing and cracking, resulting in higher breakdown voltages for semiconductor devices and cost savings by allowing production on larger substrates, enhancing the manufacturability and performance of gallium nitride-based circuits.
Implementation Method 1
This is due to a number of factors, including large thermal expansion coefficient mismatches and wafer bowing. More specifically, a gallium nitride epitaxial layer can contract about twice as fast when cooled compared to an underlying silicon substrate.
Data Source
Figure 1~2B
Figure 2C~2D
Figure 3A~3B
AI summary
A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.