GaN Amorphous Buffer Structure for Warp-Resistant Thick Layers
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Solution Overview
Problem
Gallium nitride (GaN) semiconductor devices experience significant deformation issues due to thermal and lattice mismatch with silicon-based substrates, leading to warping and cracking, particularly in thick GaN layer devices, which are not adequately addressed by existing buffer layers.
Innovation Solution
A multi-layered structure comprising amorphous layers with contrasting thermal expansion coefficients is applied to the semiconductor substrate, with the first layer having a higher CTE than the substrate and the second layer having a lower CTE, deposited at specific temperatures to mitigate deformation during processing and cooling steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If thick GaN layers are deposited on silicon-based substrates, then device performance and power handling capability are improved, but warping and cracking occur due to thermal expansion mismatch
Solution Approach 1:
The patent segments the buffer layer into multiple distinct layers with different compositions and thermal expansion coefficients. The first buffer layer has a CTE matched to the silicon substrate, while the second buffer layer has a CTE matched to the GaN layer, creating an intermediate transition zone that prevents cracking and warping in thick GaN devices
Solution Approach 2:
The patent changes the thermal expansion coefficient parameter across the buffer layer structure by using different materials (silicon oxide for the first layer, silicon nitride for the second layer) to create a gradual transition from substrate CTE to GaN CTE, thereby resolving the thermal mismatch problem
2Reliability
If buffer layers are added to reduce deformation, then warping and cracking are reduced, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent uses parameter changes by selecting materials with specific thermal expansion coefficients for each buffer layer. The first buffer layer uses silicon oxide with CTE matched to silicon substrate, and the second buffer layer uses silicon nitride with CTE matched to GaN, creating an effective stress-matched structure that reduces complexity
Solution Approach 2:
The patent introduces intermediate buffer layers that act as mediators between the silicon substrate and GaN layer. These intermediate layers with graded CTE values reduce the abrupt mismatch, thereby reducing warping and cracking while maintaining manufacturability
3Ease of manufacture
If single-layer buffer structures are used, then manufacturing is simpler, but deformation compensation is insufficient for thick GaN layers
Solution Approach 1:
The patent segments the buffer structure into multiple layers with different CTE characteristics. The first buffer layer compensates for substrate-GaN mismatch, while the second buffer layer provides additional stress relief, achieving superior deformation control for thick GaN layers
Solution Approach 2:
The patent uses composite buffer layer structures combining different materials (silicon oxide, silicon nitride) with complementary CTE properties to create a multi-functional buffer system that provides both mechanical support and thermal expansion compensation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces process and final deformation of GaN semiconductor devices, minimizing bowing and warping, and ensuring the structural integrity of the devices, even for thick GaN layers, by offsetting thermal expansion differences and lattice mismatch stresses.
Implementation Method 1
Gallium Nitride has a different thermal expansion coefficient (CTE) than many of the silicon-based substrate materials it is commonly deposited on. This means that the rate of expansion of the GaN material during heating or cooling will differ from the rate of expansion of the substrate material.
Implementation Method 2
forming at least one multi-layered structure on at least one surface(s) a semiconductor substrate and depositing a gallium nitride (GaN) semiconductor layer on the semiconductor substrate
Implementation Method 3
applying a first amorphous layer on the at least one surface(s) of the semiconductor substrate
Data Source
AI summary
Methods and structures for reducing process and final deformation of gallium nitride (GaN) semiconductor devices are provided. The methods include forming at least one multi-layered structure on at least one surface(s) a semiconductor substrate. The multi-layered structure(s) are formed by applying at least a first amorphous layer on at least one surface(s) of the semiconductor substrate, the first amorphous layer having a first thermal expansion coefficients (CTE), and applying a second amorphous layer on the first amorphous layer, the second amorphous layer having a second thermal expansion coefficient, different from the first thermal expansion coefficient.