GaN Heterojunction Transistor C-Axis Channel Carrier Control
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Solution Overview
Problem
Conventional AlGaN/GaN heterojunctions on C-plane achieve high sheet carrier density due to polarization, but struggle with accurate impurity doping and control of pinch-off voltage, while devices on A-plane or M-plane face residual carrier density issues affecting device characteristics.
Innovation Solution
A semiconductor device structure featuring a first hexagonal crystal layer with a main surface parallel to the C-axis and a second layer with a different band gap energy, where the active region's length direction is parallel to the C-axis, reducing piezo-charge generation and enabling precise carrier density control through impurity doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If AlGaN/GaN heterojunction is formed on C-plane to utilize polarization effect, then sheet carrier density increases, but pinch-off voltage control becomes difficult
Solution Approach 1:
The invention changes the crystal plane parameter from conventional C-plane to a specific tilted plane (e.g., 10-80 degrees from C-plane), which fundamentally alters the polarization characteristics and piezoelectric stress distribution. This parameter change enables simultaneous achievement of high sheet carrier density and controllable pinch-off voltage by optimizing the balance between polarization-induced carriers and doping-controlled carriers.
Solution Approach 2:
The invention employs a composite heterostructure combining AlGaN and GaN layers with specific composition ratios and thicknesses on the tilted crystal plane. By carefully designing the Al composition gradient and layer stacking sequence, the structure achieves both high carrier density from polarization and precise pinch-off control from optimized doping profiles.
2Reliability
If AlGaN/GaN heterojunction is formed on A-plane or M-plane with gate direction perpendicular to C-axis, then carrier dispersion due to dislocation is reduced, but residual carrier density increases
Solution Approach 1:
The invention introduces a tilted plane parameter (10-80 degrees from C-plane) that optimizes the balance between dislocation alignment and piezoelectric stress. This angular parameter adjustment reduces carrier dispersion by improving crystal quality while simultaneously managing residual carrier density through controlled piezoelectric charge generation in the tilted structure.
Solution Approach 2:
The invention creates local quality variations by implementing different Al compositions and doping concentrations in specific regions of the tilted plane structure. This allows optimization of carrier density and distribution in the active region while managing residual carriers through localized compositional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure allows for accurate control of carrier density, suppressing piezo-charge and enhancing device characteristics, such as low voltage and current thresholds in FETs and semiconductor laser devices, while maintaining high crystallinity and reducing residual carrier density.
Implementation Method 1
The mechanism of carrier generation is that two-dimensional electrons are accumulated in a boundary between AlGaN and GaN, which is caused by a polarization generated due to a piezo effect in the AlGaN layer because of the stress between AlGaN and GaN due to the lattice mismatch
Data Source
AI summary
A semiconductor device, which can accurately control carrier density, includes: a single crystal substrate; a semiconductor layer which is made of hexagonal crystal with 6 mm symmetry and is formed on the single crystal substrate; a source electrode, a drain electrode and a gate electrode which are formed on the semiconductor layer, where the main surfaces of a GaN layer and an AlGaN layer constituting the semiconductor layer respectively include C-axis of the hexagonal crystal, and a length direction of a channel region in the semiconductor layer is parallel to the C-axis of the hexagonal crystal.