GaN Semiconductor Cap Layer Cracking Prevention

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Solution Overview

Problem

The existing manufacturing methods for semiconductor devices using GaN substrates face issues with cracking due to thermal expansion differences between the cap/block layer and the coating layer, leading to surface damage during heat treatment, especially when the substrate size exceeds 1 inch.

Innovation Solution

A manufacturing method involving the formation of a cap layer mainly composed of a nitride, followed by ion implantation of a p-type impurity, and the creation of a block layer with a higher coefficient of thermal expansion than the cap layer, which is used as a surface layer during heat treatment to activate the p-type impurity, thereby reducing the likelihood of cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a cap layer and coating layer are formed on a large-sized GaN substrate, then the substrate can be protected during heat treatment, but cracking occurs due to thermal expansion differences between layers

Engineering Contradiction:
Improveprotection of GaN substrate surfaceVSAvoidcracking resistance of cap layer
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The cap layer is divided into multiple sub-layers with different materials and thermal expansion coefficients. The first cap layer has a thermal expansion coefficient closer to the GaN substrate, while the second cap layer has a thermal expansion coefficient closer to the coating layer, creating a gradient structure that reduces stress concentration and prevents cracking during heat treatment of large substrates

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the cap layer structure are assigned different material compositions and thermal expansion properties. The first cap layer region is optimized for substrate bonding with lower thermal expansion, while the second cap layer region is optimized for coating layer interface with higher thermal expansion, allowing each region to locally accommodate thermal stresses

Inventive Principle:
Principle #3Local quality

2Reliability

If the cap layer thermal expansion coefficient is matched to the substrate, then substrate protection is improved, but the coating layer interface stress increases

Engineering Contradiction:
Improvesubstrate protection during heat treatmentVSAvoidinterface stress between cap layer and coating layer
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The thermal expansion coefficient parameter is varied across different cap layer regions. The first cap layer uses materials with thermal expansion coefficients matched to the GaN substrate, while the second cap layer uses materials with thermal expansion coefficients matched to the coating layer, creating a parameter gradient that simultaneously protects the substrate and reduces interface stress

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively minimizes cracking and protects the surface of the GaN substrate during heat treatment, even for larger substrate sizes, by managing thermal expansion stresses through the use of a cap and block layer with specific thermal expansion coefficients.

Implementation Method 1

forming a block layer having a larger coefficient of thermal expansion than a coefficient of thermal expansion of the cap layer, as a surface layer on the cap layer; heating the semiconductor layer with the block layer as the surface layer

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

implanting a p-type impurity into the semiconductor layer with at least part of the cap layer formed thereon, by ion implantation

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS10083918B2Manufacturing method of semiconductor device
Publication Date: 2018.09.25 TOYODA GOSEI CO LTD
  • US10083918B2 patent drawing
  • US10083918B2 patent drawing
  • US10083918B2 patent drawing

AI summary

There is provided a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device comprises: forming at least part of a cap layer that is mainly composed of a nitride, on a semiconductor layer that is mainly composed of a group III nitride semiconductor; implanting a p-type impurity into the semiconductor layer with at least part of the cap layer formed thereon, by ion implantation; forming a block layer having a larger coefficient of thermal expansion than a coefficient of thermal expansion of the cap layer, as a surface layer on the cap layer; and heating the semiconductor layer with the block layer as the surface layer, to activate the p-type impurity.