GaN Cascode Gate Structure for Lower Feedback Capacitance
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Solution Overview
Problem
High power and high frequency semiconductor devices face challenges with charge trapping and reliability issues due to high electric fields, particularly in GaN-based HEMTs, which affect their performance and linearity, especially in class C operation and high power RF applications.
Innovation Solution
A dual-gate transistor or cascode structure with a cap layer made of GaN separates the second stage gate from the barrier layer, eliminating the need for separate DC biasing of the second gate, thereby reducing feedback capacitance and improving linearity while maintaining cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a field plate is connected to the gate on the drain side to reduce electric field and increase breakdown voltage, then reliability improves, but gate-to-drain capacitance increases and linearity deteriorates
Solution Approach 1:
The device is divided into two separate gates: a first gate for controlling the channel and a second gate for field plate functionality. This segmentation allows each gate to be optimized for its specific function, with the second gate positioned to reduce gate-to-drain capacitance while maintaining breakdown voltage protection.
Solution Approach 2:
The field plate function is extended into a new dimensional configuration by adding a second gate that can be positioned in different spatial arrangements (above, beside, or overlapping the first gate). This dimensional flexibility enables optimization of both breakdown voltage and capacitance characteristics simultaneously.
2Object-generated harmful factors
If a second gate is added to reduce feedback capacitance and improve linearity, then performance improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The second gate serves multiple functions simultaneously: it acts as a field plate to reduce gate-to-drain capacitance, provides additional channel control capability, and can function as a separate control terminal for different operating modes. This multi-functionality justifies the added structure by delivering multiple performance benefits from a single additional element.
Solution Approach 2:
The second gate is integrated with the first gate structure through shared semiconductor layers and common fabrication processes. The gates can be positioned in various configurations (overlapping, adjacent, or stacked) that merge their functional regions while maintaining electrical independence, thereby reducing the incremental complexity compared to fully separate structures.
3Reliability
If silicon nitride passivation is applied to reduce electron trapping, then reliability improves, but high electric field charge trapping persists
Solution Approach 1:
The second gate acts as an intermediary element that modifies the electric field distribution in the region where charge trapping occurs. By positioning the second gate to create a more uniform electric field, the peak fields that cause charge trapping in the passivation layer are reduced, thereby preventing trapping effects even when SiN passivation is present.
Solution Approach 2:
The second gate is positioned and biased to preemptively counteract the formation of high electric fields that would cause charge trapping. By establishing a favorable field distribution before trapping can occur, the structure prevents the harmful effect rather than addressing it after the fact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides lower feedback capacitance and improved linearity with reduced complexity and cost, enabling high voltage, high current, and high gain operation in GaN-based HEMTs, addressing the reliability and performance issues associated with charge trapping.
Implementation Method 1
A dual-gate transistor or cascode structure with a cap layer made of GaN separates the second stage gate from the barrier layer, eliminating the need for separate DC biasing of the second gate, thereby reducing feedback capacitance
Implementation Method 2
In a HEMT device, a two-dimensional electron gas (2DEG) may be formed at the heterojunction of two semiconductor materials with different bandgap energies
Implementation Method 3
A major portion of the electrons in the 2DEG may be attributed to polarization in the AlGaN
Data Source
Figure 1A~1D
Figure 1C~3
Figure 4~6
AI summary
A transistor device including a cap layer is described. One embodiment of such a device includes cap layer between a gate and a semiconductor layer. In one embodiment, the thickness of the cap layer is between 5nm and 1OOnm. In another embodiment, the cap layer can be doped, such as delta-doped or doped in a region remote from the semiconductor layer. Devices according to the present invention can show capacitances which are less drain bias dependent, resulting in improved linearity.