GaN Cascode FET Circuit for Low Power Enhancement Mode Operation
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Solution Overview
Problem
Conventional GaN-based FETs operate as depletion-mode devices, requiring continuous gate bias to maintain the off state, leading to excessive power consumption, whereas the goal is to achieve enhancement-mode operation for reduced power usage, but existing attempts at manufacturing GaN-based enhancement-mode FETs have been unsatisfactory due to poor on-state conductance and breakdown voltages.
Innovation Solution
A circuit is designed by combining a GaN-based depletion-mode FET with an enhancement-mode FET, where the source of the depletion-mode FET is serially coupled to the drain of the enhancement-mode FET, and the gate of the depletion-mode FET is grounded to maintain the on-state, allowing the enhancement-mode FET to modulate current and provide blocking capability, effectively acting as a high-voltage enhancement-mode device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a depletion-mode GaN-based FET is used, then high breakdown voltage and electron mobility are achieved, but continuous gate bias is required to maintain off state leading to excessive power consumption
Solution Approach 1:
The invention segments the FET into two independent gates: a first gate (conventional gate) and a second gate (back gate). The first gate controls the primary current flow, while the second gate provides bias control to maintain the off state without continuous power consumption. This segmentation allows the device to achieve enhancement-mode operation while retaining the high breakdown voltage characteristics of depletion-mode GaN FETs.
Solution Approach 2:
The invention changes the operational parameters by introducing a dual-gate configuration where the second gate can adjust the threshold voltage and channel conductivity. By controlling the voltage applied to the second gate, the device can be maintained in the off state without continuous bias to the first gate, thereby reducing power consumption while maintaining reliable off-state performance.
2Use of energy by moving object
If an enhancement-mode GaN-based FET is manufactured, then power consumption is reduced, but on-state conductance and breakdown voltage deteriorate
Solution Approach 1:
The dual-gate structure segments the control functions: the first gate maintains high breakdown voltage capability through its Schottky contact configuration, while the second gate enhances the off-state performance and reduces power consumption. This segmentation allows both enhancement-mode power efficiency and depletion-mode high voltage characteristics to coexist.
Solution Approach 2:
The invention employs a composite structure with a GaN-based semiconductor layer having a first region (under the first gate) and a second region (under the second gate). This composite material approach allows different regions to be optimized for different functions: one region for high voltage blocking and another for low-power operation, achieving both high breakdown voltage and reduced power consumption simultaneously.
3Use of energy by moving object
If an enhancement-mode GaN-based FET is manufactured, then power consumption is reduced, but on-state conductance deteriorates
Solution Approach 1:
The segmentation of gate control functions allows the first gate to maintain optimal on-state conductance through conventional gating mechanisms, while the second gate provides additional control to reduce off-state leakage and power consumption. This segmented approach enables independent optimization of both on-state and off-state characteristics.
Solution Approach 2:
The second gate serves multiple functions: it can enhance the off-state blocking capability, reduce power consumption, and also provide additional control over the on-state conductance. This multi-functionality allows the device to achieve both low power consumption and high on-state conductance by appropriately controlling the voltage on the second gate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The combined device achieves the desired enhancement-mode operation with improved power efficiency, maintaining the on-state without continuous gate voltage application, and exhibits high input impedance, low noise, and high gain, while maintaining the characteristics of the depletion-mode FET, such as high breakdown voltage.
Implementation Method 1
The GaN-based FET device is capable of maximizing electron mobility by forming a quantum well at the heterojunction interface between the AlGaN layer, which has a large band gap, and the GaN layer, which has a narrower band gap. As a result, electrons are trapped in the quantum well.
Implementation Method 2
The trapped electrons are represented by a two-dimensional electron gas 96 in the undoped GaN layer.
Implementation Method 3
Even when the gate voltage is zero, electrons will be present in the channel because a piezoelectric field is formed that extends from the substrate toward the device surface.
Data Source
AI summary
A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.