GaN Cascode Transistor Gate Voltage Control
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Solution Overview
Problem
GaN-based transistors used in power circuits face challenges in achieving normally-off operation due to the difficulty in realizing a sufficient on-state current flow, especially when connected in cascode configurations with Si transistors, leading to reliability issues and current collapse.
Innovation Solution
A semiconductor device configuration that includes an N-ch normally-off transistor and an N-ch normally-on transistor connected in series, with a level shift element, such as a zener diode, to manage the gate voltage and prevent overvoltage, ensuring the normally-off transistor's avalanche breakdown voltage is lower than the normally-on transistor's gate insulating film withstand voltage, thereby enhancing reliability and current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normally-on GaN based transistor is connected in cascode with a normally-off Si transistor, then normally-off operation is achieved, but the gate voltage of the GaN transistor cannot be made sufficiently high, resulting in insufficient on-state current
Solution Approach 1:
The invention divides the gate control into two independent gates: a first gate for the Si transistor and a second gate for the GaN transistor. This segmentation allows independent optimization of each transistor's gate voltage, enabling the GaN transistor to receive sufficient gate voltage for high on-state current while maintaining normally-off operation through the Si transistor's control
Solution Approach 2:
The invention introduces a level shift element as an intermediary between the first gate and the second gate. This level shift element transforms the voltage signal from the first gate to an appropriate level for the second gate, enabling proper voltage matching and current flow control in the cascode configuration
2Reliability
If the avalanche breakdown voltage of the normally-off transistor is made lower than the gate insulating film withstand voltage of the normally-on transistor, then reliability is improved by preventing gate insulating film breakdown, but device complexity increases
Solution Approach 1:
The invention establishes preliminary voltage protection by designing the avalanche breakdown voltage of the Si transistor to be lower than the gate insulating film withstand voltage of the GaN transistor. This preliminary voltage limitation prevents excessive voltage from reaching the GaN transistor's gate, protecting against gate insulating film breakdown before it can occur
Solution Approach 2:
The invention optimizes the voltage parameters of the cascode structure by setting specific relationships between the avalanche breakdown voltage of the Si transistor and the gate insulating film withstand voltage of the GaN transistor. This parameter optimization ensures reliable voltage protection while maintaining efficient current flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed configuration ensures reliable operation by preventing gate insulating film breakdown and current collapse, allowing for efficient on-state current flow and improved reliability in power modules.
Implementation Method 1
a level shift element, such as a zener diode, to manage the gate voltage and prevent overvoltage
Implementation Method 2
ensuring the normally-off transistor's avalanche breakdown voltage is lower than the normally-on transistor's gate insulating film withstand voltage
Data Source
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AI summary
A semiconductor device according to an embodiment is provided with a normally-off transistor (10) which includes a first source (11) connected to a source terminal (100), a first drain (12), and a first gate (13) connected to a gate terminal (300), and a normally-on transistor (20) which includes a second source (21) connected to the first drain (12), a second drain (22) connected to a drain terminal (200), and a second gate (23) connected to the gate terminal (300).