GaN CAVET Structure With Diffusion Blocking for Current Collapse
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Solution Overview
Problem
Conventional GaN-based current aperture vertical electron transistors (CAVETs) face issues with doping out-diffusion, material quality degradation, and high thermal budgets during drain contact formation, limiting their performance and reliability.
Innovation Solution
The CAVET design incorporates a semiconductor superlattice as a diffusion blocking layer to prevent dopant out-diffusion, uses a graded carbon-doped GaN layer to suppress electron trapping, and employs an engineered SiC substrate for annealing-free drain contact formation, enhancing material quality and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type GaN layer is used as a current blocking layer to prevent dopant out-diffusion, then dopant diffusion is suppressed, but Mg out-diffusion still occurs into the channel layer causing current collapse
Solution Approach 1:
The patent employs a hybrid blocking layer structure consisting of p-GaN and carbon-doped GaN layers. The p-GaN layer provides electrical blocking functionality while the carbon-doped GaN layer suppresses Mg out-diffusion through carbon's strong bonding characteristics, creating a composite structure that addresses both requirements simultaneously
Solution Approach 2:
The carbon-doped GaN layer acts as an intermediary between the p-GaN current blocking layer and the channel layer. It serves as a diffusion barrier that prevents Mg atoms from migrating into the channel, while also maintaining the electrical blocking function through the p-GaN layer
2Manufacturing precision
If carbon doping is used in the GaN layer to suppress Mg out-diffusion, then dopant diffusion is reduced, but material quality decreases and electron trapping occurs
Solution Approach 1:
The patent applies carbon doping locally in a specific layer (the carbon-doped GaN layer within the hybrid blocking structure) rather than throughout the entire device. This localized approach confines the diffusion-blocking function to where it is needed while minimizing the negative effects of carbon on material quality in other regions
Solution Approach 2:
The patent optimizes the carbon doping concentration and layer thickness parameters to achieve the right balance between diffusion blocking and material quality. By carefully controlling these parameters, the carbon-doped layer provides effective Mg suppression while minimizing electron trapping effects
3Manufacturing precision
If high temperature annealing is used to form Ohmic drain contact on n-type GaN substrate, then contact resistance is reduced, but thermal budget increases and damages the device
Solution Approach 1:
The patent changes the substrate doping parameter from n-type to p-type, which fundamentally alters the contact formation requirements. This parameter change enables drain contact formation at lower temperatures while achieving adequate contact resistance characteristics, thus reducing the thermal budget
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved CAVET achieves better channel quality, higher mobility, and reduced thermal stress, resulting in enhanced performance and reliability with simplified manufacturing, suitable for high-power applications.
Implementation Method 1
a diffusion blocking layer arranged on the current blocking layer, wherein the diffusion blocking layer comprises a semiconductor superlattice
Implementation Method 2
uses a graded carbon-doped GaN layer to suppress electron trapping
Data Source
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AI summary
The present disclosure relates to a current aperture vertical electron transistor (CAVET). The CAVET may be a nitride based, for example, GaN-based device. The CAVET of this disclosure comprises a current blocking layer (CBL) and a diffusion blocking layer arranged on the CBL to prevent dopant diffusion from the CBL to a channel layer. An aperture is formed in the CBL and the diffusion blocking layer, and a heterostructure including the channel layer is formed in the aperture and on the diffusion blocking layer. In an implementation of the CAVET, the diffusion blocking layer comprises a semiconductor superlattice. In another implementation of the CAVET, a substrate of the CAVET is an engineered substrate 101, which comprises a 3C-SiC polycrystalline bottom layer and a single crystalline SiC or GaN top layer arranged on the bottom layer. A backside drain contact may be formed on the substrate without using thermal annealing.