GaN Transistor Channel Layer Segmentation for Dynamic On-Resistance
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Solution Overview
Problem
Transistors with channel layers made of compound semiconductor materials, such as GaN, experience a significant increase in dynamic on-resistance at elevated temperatures, leading to higher leakage currents and reduced efficiency during on and off switching operations.
Innovation Solution
The implementation of a transistor structure that includes a carrier accumulation layer, a carrier barrier layer, and a channel layer with a compound semiconductor material, where the carrier barrier layer has a lower carrier trapping site density than conventional superlattice structures, and the carrier accumulation layer has a higher carrier impurity concentration to confine carriers within the channel layer, reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional superlattice structure is used in the channel layer, then manufacturing complexity is reduced, but dynamic on-resistance increases significantly at elevated temperatures
Solution Approach 1:
The channel layer is segmented into multiple functional layers: a first channel layer with higher carrier impurity concentration and a second channel layer with lower carrier impurity concentration. This segmentation allows each layer to perform specific functions - the first layer provides carrier accumulation to reduce on-resistance, while the second layer maintains low trapping site density to prevent leakage current, thereby resolving the contradiction between reliability and structural simplicity.
Solution Approach 2:
Different regions of the channel layer are assigned different carrier impurity concentrations to optimize local performance. The first channel layer (closer to the gate) has higher carrier impurity concentration to enhance carrier accumulation and reduce on-resistance, while the second channel layer (closer to the drain) has lower carrier impurity concentration to minimize trapping sites and reduce leakage current. This local differentiation resolves the contradiction by optimizing each region for its specific function.
2Reliability
If carrier impurity concentration is increased to reduce on-resistance, then dynamic on-resistance decreases, but leakage current increases due to more trapping sites
Solution Approach 1:
The channel layer is divided into two segments with different carrier impurity concentrations. The first channel layer has higher carrier impurity concentration to provide sufficient carriers for low on-resistance, while the second channel layer has lower carrier impurity concentration to reduce trapping site density and minimize leakage current. This segmentation resolves the contradiction by separating the functions of carrier supply and leakage prevention into different regions.
Solution Approach 2:
The channel layer exhibits non-uniform carrier impurity concentration distribution, with the first channel layer having higher concentration near the gate for carrier accumulation, and the second channel layer having lower concentration near the drain to reduce trapping. This local quality differentiation allows the structure to simultaneously achieve low on-resistance and low leakage current by optimizing each region for its primary function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the dynamic on-resistance at elevated temperatures, maintaining high efficiency and allowing more current to pass through the transistor when it is on, while minimizing leakage current when it is off.
Implementation Method 1
the carrier accumulation layer has a higher carrier impurity concentration to confine carriers within the channel layer
Implementation Method 2
A transistor can have a channel layer that includes a compound semiconductor material, such as GaN. Such transistor can have an dynamic on-resistance (RDSON) that is dramatically higher at a higher temperature, such as at 150° C.
Data Source
AI summary
An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof.