GaN Chiplet Singulation With Narrow Streets and Stretchable Tape
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Solution Overview
Problem
Current techniques lack the ability to effectively singulate sub-mm-scale GaN transistor chiplets while co-fabricating transistor vias and transferring them onto semiconductor chips with differing chemistries, such as silicon-based CMOS chips, for use in hybrid integrated circuits.
Innovation Solution
A method involving the singulation of GaN transistor chiplets from a wafer with streets less than 50 μm wide, etching backside vias simultaneously, and transferring them onto stretchable tape compatible with pick-and-place tools, allowing for increased spacing and efficient integration into cavities within semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dicing technologies are used to separate chiplets, then chiplets can be singulated, but the streets between chiplets become too wide which reduces packing density
Solution Approach 1:
The patent segments the dicing process into multiple stages: first forming a mandrel pattern, then depositing a first etch mask, performing a first etch to create initial streets, removing the first etch mask, depositing a second etch mask, and performing a second etch to complete the street formation. This multi-stage segmentation enables precise control of street widths down to 50 micrometers or less, significantly improving packing density compared to conventional single-stage dicing.
2Ease of manufacture
If sub-mm-scale GaN transistor chiplets are manufactured on a single wafer, then manufacturing cost is reduced, but the number of chiplets per wafer is limited by street width requirements
Solution Approach 1:
The patent performs preliminary actions by forming mandrels, depositing etch masks, and etching streets while the chiplets are still connected on the wafer, before the actual singulation and pick-and-place operations. This preliminary street formation with precise width control enables higher chiplet density on each wafer, allowing more chiplets to be manufactured simultaneously at reduced cost.
3Adaptability or versatility
If chiplets are placed into cavities and electrically connected, then hybrid integrated circuits are formed, but the process complexity increases
Solution Approach 1:
The patent uses stretchable tape as an intermediary carrier that simplifies the placement process. Chiplets are transferred to the stretchable tape in array form, and the tape's elasticity allows it to be stretched during pick-and-place operations, enabling easy manipulation and placement of multiple chiplets into cavities on the device wafer. This intermediary carrier significantly reduces the complexity of handling and placing individual sub-mm-scale chiplets.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-yield singulation and transfer of GaN transistor chiplets with backside vias onto stretchable tape, facilitating their placement into cavities within semiconductor chips, thereby enhancing the packing density and reducing manufacturing costs for hybrid integrated circuits.
Implementation Method 1
The streets and backside vias are etched through the GaN wafer using a plasma process
Data Source
AI summary
An array of III-V material transistors singulated from a Si or SiC wafer disposed on a stretchable tape compatible with pick and place tools and a method of forming same.