GaN Cascode Switch Clamp Circuit for Avalanche Protection
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Solution Overview
Problem
Cascoded power semiconductor devices face challenges with electrical current leakage and reliability due to the 'normally-on' behavior of Gallium Nitride (GaN) power switches, which can lead to avalanche currents and gate isolation breakdown, especially when switching off, requiring additional layers that compromise device performance.
Innovation Solution
Incorporating a clamp-circuit between the depletion-source-terminal and depletion-gate-terminal, which can be a diode circuit, including Schottky diodes, to limit voltage and prevent avalanche currents, integrated on the same semiconductor die as the insulated-gate-depletion-mode-transistor, thereby enhancing the reliability and energy efficiency of the cascode power switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cascode configuration with GaN depletion-mode transistor is used, then switching speed and power handling capability are improved, but electrical current leakage and reliability deteriorate due to normally-on behavior
Solution Approach 1:
The clamp circuit acts as an intermediary protective element between the GaN depletion-mode transistor and the enhancement-mode transistor. It mediates the voltage distribution during switching transitions, preventing harmful voltage spikes from reaching the enhancement-mode transistor's gate while maintaining the high-speed switching capability of the GaN device.
Solution Approach 2:
The clamp circuit is pre-configured with a breakdown voltage lower than the enhancement-mode transistor's gate breakdown voltage. During normal operation, it remains inactive but is ready to activate immediately when voltage exceeds the clamp threshold, preventing damage before it occurs. This preliminary protective action eliminates the need for additional protective layers that would compromise device performance.
2Reliability
If additional protective layers are added to prevent avalanche currents, then reliability is improved, but device performance deteriorates
Solution Approach 1:
The clamp circuit serves as a dedicated protective intermediary that handles avalanche current suppression without requiring modifications to the main power switching structure. By placing the clamp in parallel with the enhancement-mode transistor gate, it provides protection while maintaining the original device's high-frequency switching performance and low on-resistance characteristics.
Solution Approach 2:
The clamp circuit changes the voltage parameter distribution across the cascode structure by clamping the gate-source voltage of the enhancement-mode transistor to a safe level. This parameter control prevents avalanche breakdown while allowing the main power devices to operate at their optimal performance parameters without additional protective layers.
3Reliability
If the clamp circuit breakdown voltage is set below enhancement-mode transistor gate breakdown voltage, then protection effectiveness is improved, but voltage utilization deteriorates
Solution Approach 1:
The clamp circuit's breakdown action, which might seem to limit voltage utilization, actually converts potentially harmful high-voltage transients into controlled, safe voltage levels. The 'harm' of voltage limitation is transformed into the 'benefit' of reliable gate protection, preventing catastrophic failures while the main power devices continue to handle the full power voltage through their drain-source terminals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The clamp-circuit effectively limits voltage across the enhancement-mode transistor, preventing avalanche currents and improving the reliability of both the enhancement-mode and depletion-mode transistors, reducing the need for cooling and enhancing energy efficiency by minimizing electrical leakage.
Implementation Method 1
prevent avalanche currents
Implementation Method 2
the diode circuit may comprise a Schottky diode
Data Source
AI summary
A semiconductor device comprising: a die-source-terminal, a die-drain-terminal and a die-gate-terminal; a semiconductor-die; an insulated-gate-depletion-mode-transistor provided on the semiconductor-die, the insulated-gate-depletion-mode-transistor comprising a depletion-source-terminal, a depletion-drain-terminal and a depletion-gate-terminal, wherein the depletion-drain-terminal is coupled to the die-drain-terminal and the depletion-gate-terminal is coupled to the die-source-terminal; an enhancement-mode-transistor comprising an enhancement-source-terminal, an enhancement-drain-terminal and an enhancement-gate-terminal, wherein the enhancement-source-terminal is coupled to the die-source-terminal, the enhancement-gate-terminal is coupled to the die-gate-terminal and the enhancement-drain-terminal is coupled to the depletion-source-terminal; and a clamp-circuit coupled between the depletion-source-terminal and the depletion-gate-terminal.