GaN-CMOS Co-Integrated Circuit Layout for Compact Power and RF
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Solution Overview
Problem
Si and group III-V technologies face fundamental limits in power and RF performance, necessitating a better semiconductor technology for advanced compute solutions that require higher energy efficiency, better performance, and more functionalities in smaller form factors.
Innovation Solution
Co-integration of gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuits through on-die integration with thick germanium-rich layers and trench etching, enabling compact power delivery and RF solutions by combining GaN devices with CMOS logic on a single die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Si and group III-V technologies are used for power delivery and RF, then power and RF performance can be achieved, but fundamental limits are reached that prevent further improvement in energy efficiency, performance, and functionality
Solution Approach 1:
The patent combines GaN power/RF devices with CMOS logic devices into a single co-integrated circuit on one semiconductor die. This merging allows the system to overcome the fundamental limits of separate Si and group III-V technologies by integrating the high power/RF capability of GaN with the high-speed logic capability of CMOS, enabling improved energy efficiency and functionality while maintaining reliability.
2Reliability
If separate GaN devices and CMOS logic are used, then power delivery and RF functions can be implemented, but the form factor increases and compact integration is lost
Solution Approach 1:
The patent merges GaN power/RF devices and CMOS logic devices into a single co-integrated circuit structure on one semiconductor die. This integration dramatically reduces the form factor compared to using separate discrete devices or separate chips, while maintaining all necessary power delivery and RF functionalities through monolithic integration.
3Ease of manufacture
If conventional integration methods are used, then manufacturing simplicity is maintained, but the ability to achieve advanced co-integration of GaN and CMOS on a single die is limited
Solution Approach 1:
The patent segments the integration process into distinct stages: first forming GaN devices on a first portion of the semiconductor die, then forming CMOS logic devices on a second portion of the same die. This segmented approach allows each device type to be manufactured using its optimal process conditions while achieving advanced co-integration, balancing manufacturing simplicity with enhanced adaptability.
Data Source
AI summary
Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.