GaN CMOS Integration via Segmented Barrier Layers

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Solution Overview

Problem

Current semiconductor technologies lack the integration of high-performance P-channel GaN transistors with N-channel GaN transistors on the same substrate, hindering the development of efficient GaN-based complementary metal-oxide-semiconductor (CMOS) integrated circuits.

Innovation Solution

A method is developed to form III-nitride (III-N) layer buffer layers, N-channel and P-channel layers, and dielectric layers on a substrate, with ion implantation for isolation, enabling the monolithic integration of N-channel and P-channel transistors on a common substrate, forming a GaN-based CMOS integrated circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If GaN N-channel transistors are used, then high-power and high-frequency performance is achieved, but P-channel GaN transistor integration is not possible

Engineering Contradiction:
Improvehigh-power performanceVSAvoidP-channel transistor integration
Core Design Contradiction:
PowerVSAdaptability or versatility

Solution Approach 1:

The patent divides the semiconductor structure into distinct N-channel and P-channel transistor regions, each with their own channel layers and barrier layers. The N-channel transistor comprises an N-channel layer with N-barrier layer, while the P-channel transistor comprises a P-channel layer with P-barrier layer, allowing both types to coexist on the same substrate without interference

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different doping types and material compositions to different regions of the semiconductor structure. The N-channel region uses n-type doping while the P-channel region uses p-type doping. Additionally, different barrier layer compositions (AlGaN for N-channel, AlInGaN for P-channel) are used locally to optimize each transistor type's performance characteristics

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If P-channel GaN transistor is added to achieve CMOS integration, then complementary logic functionality is enabled, but device complexity increases

Engineering Contradiction:
Improvecomplementary logic functionalityVSAvoidmulti-layer heterostructure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines N-channel and P-channel transistor fabrication into a single monolithic growth process using molecular beam epitaxy (MBE). Both transistor types are formed simultaneously in different regions of the same substrate, sharing common buffer layers and utilizing the same manufacturing equipment and process steps, thereby reducing overall fabrication complexity despite the multi-layer structure

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The AlGaN buffer layer serves multiple functions: it provides a lattice-matched substrate for both N-channel and P-channel transistor growth, acts as a barrier to dislocation propagation, and enables the formation of both n-type and p-type channel layers. This multi-functional design simplifies the overall device architecture while maintaining high performance

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in high-performance GaN-based CMOS integrated circuits with improved power consumption and functionality, surpassing discrete transistor circuits and Si CMOS performance by enabling the integration of N-channel and P-channel transistors on a common substrate.

Implementation Method 1

implanting ions in the buffer layer between the first mesa and the second mesa for providing isolation between the N-channel transistor and the P-channel transistor

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentEP3345216B1Iii nitride complementary transistors
Publication Date: 2021.10.13 HRL LAB
  • EP3345216B1 patent drawingFigure 1
  • EP3345216B1 patent drawingFigure 2A~2C
  • EP3345216B1 patent drawingFigure 2D~2F

AI summary

A semiconductor device includes a substrate, a III- nitride buffer layer on the substrate, an N-channel transistor including a Ill-nitride N-channel layer on one portion of the buffer layer, and a Ill-nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N-barrier layer has a wider bandgap than the N-channel layer, a P-channel transistor including a Ill-nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes, a III- nitride P-channel layer on top of the P-barrier layer, wherein the P-barrier layer has a wider bandgap than the P- channel layer, and a Ill-nitride cap layer doped with P- type dopants on top of the P-channel layer.