Composite High-k Metal Gate Stack for GaN Enhancement Mode Devices
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Solution Overview
Problem
Conventional mobile computing platforms face challenges in integrating power management ICs (PMIC) and RFICs due to incompatible transistor technologies, which limit scalability, power efficiency, and form factor, primarily due to lattice mismatch and thermal expansion issues in III-N material heteroepitaxy on silicon substrates, and high junction leakage in multi-gate transistors.
Innovation Solution
A composite high-k metal gate stack for enhancement mode gallium nitride (GaN) transistors is developed, featuring a tri-layer gate dielectric stack with a high band gap Group III-N layer and a combination of higher and lower k high-k oxide layers, along with sulfur- and fluoride-based treatments to achieve low gate leakage and near-ideal gate-oxide interfaces, enabling compatible operation for both PMIC and RFIC functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heteroepitaxy of III-N material stacks on silicon substrates is performed, then high breakdown voltage and high gain cutoff frequency can be obtained, but significant lattice mismatch and thermal expansion mismatch lead to high defect densities and poor device performance
Solution Approach 1:
The patent segments the gate dielectric into a multi-layer stack structure comprising a first gate dielectric layer and a second gate dielectric layer. The first layer (AlInN) provides a high-quality interface with the GaN channel, while the second layer (high-k oxide) provides high capacitance for enhancement mode operation. This segmentation allows each layer to optimize for its specific function, reducing overall device defects while maintaining performance.
Solution Approach 2:
The patent employs composite materials by combining AlInN and high-k oxide materials in a layered gate dielectric structure. The AlInN layer provides lattice-matched growth with GaN and low defect density at the interface, while the high-k oxide layer provides the necessary dielectric properties for enhancement mode operation. This composite approach allows the device to achieve both low defect density and high performance.
2Ease of manufacture
If conventional gate dielectric structures are used in GaN transistors, then fabrication is simpler, but gate leakage is high and enhancement mode operation is difficult to achieve
Solution Approach 1:
The gate dielectric is segmented into two functional layers: the AlInN layer that forms a low-defect interface with GaN and provides structural stability, and the high-k oxide layer that provides high dielectric constant for low gate leakage and enhancement mode operation. This segmentation enables each layer to address specific challenges without compromising the other.
Solution Approach 2:
The patent changes the dielectric constant parameter by introducing high-k oxide material in the second gate dielectric layer. This parameter change enables the transistor to achieve enhancement mode operation with low gate leakage, as the high-k material provides stronger electric field confinement and reduces tunneling current through the dielectric.
3Device complexity
If single-layer gate dielectric is used, then device structure is simpler, but interface quality and gate leakage control are insufficient
Solution Approach 1:
The gate dielectric is divided into two specialized layers: AlInN for interface quality and high-k oxide for electrical performance. This segmentation allows optimization of interface quality without excessive complexity, as each layer has a clearly defined function and can be deposited using standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the fabrication of GaN transistors suitable for enhancement mode operation with low gate leakage and near-ideal subthreshold slope, addressing the integration challenges and improving power efficiency and scalability for mobile computing platforms.
Implementation Method 1
a high band gap Group III-N layer and a composite high-K oxide portion
Implementation Method 2
composite high-K oxide portion comprising a first high-K oxide layer and a second high-K oxide layer
Implementation Method 3
sulfur- and fluoride-based treatments to achieve low gate leakage and near-ideal gate-oxide interfaces
Data Source
Figure 1A~1B
Figure 1C
Figure 2A
AI summary
Enhancement mode gallium nitride (GaN) semiconductor devices having a composite high-k metal gate stack and methods of fabricating such devices are described. In an example, a semiconductor device includes a gallium nitride (GaN) channel region disposed above a substrate. A gate stack is disposed on the GaN channel region. The gate stack includes a composite gate dielectric layer disposed directly between the GaN channel region and a gate electrode. The composite gate dielectric layer includes a high band gap Group III-N layer, a first high-K dielectric oxide layer, and a second high-K dielectric oxide layer having a higher dielectric constant than the first high-K dielectric oxide layer. Source/drain regions are disposed on either side of the GaN channel region.