GaN HEMT Contact Resistance via CMOS-Compatible Binary Layer Annealing
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Solution Overview
Problem
Current CMOS compatible metal processes for GaN/AlGaN systems face challenges such as high ohmic resistance at source and drain contacts, electrical shorts, and the inability to perform self-aligned silicidation/germanidation due to the nature of GaN/AlGaN/metal systems, which are costly and inefficient compared to gold-based processes.
Innovation Solution
A method is developed for fabricating semiconductor devices using an Au-free CMOS compatible self-aligning process that involves growing nucleation layers, depositing binary layers with group 14 elements like Si or Ge, and annealing to form contact areas with reduced resistance, allowing for improved contact resistance and integration with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold-based processes are used for GaN/AlGaN contacts, then contact resistance is reduced, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive gold-based contact materials with cheaper CMOS-compatible metals (such as tungsten, cobalt, or nickel) that can be deposited using standard CMOS fabrication processes. This substitution directly addresses the cost issue while maintaining acceptable contact resistance performance through optimized metal layer structures and annealing processes.
Solution Approach 2:
The patent employs annealing processes to modify the physical and chemical properties of the CMOS-compatible metal layers, transforming them into low-resistance contact structures. By controlling annealing temperature, time, and atmosphere, the metal layers develop favorable electrical properties that approach or match gold-based contacts, thereby resolving the contradiction between cost and performance.
2Manufacturing precision
If conventional self-aligned silicidation process is used, then manufacturing precision is improved, but electrical shorts occur between gate source and drain
Solution Approach 1:
The patent introduces an intermediate metal layer or dielectric spacer between the gate and source/drain regions during the self-aligned process. This intermediary element prevents direct electrical contact between gate and source/drain while maintaining the self-alignment advantage, thereby resolving the electrical short issue without sacrificing manufacturing precision.
Solution Approach 2:
The patent applies different material properties or structural characteristics to different regions of the device. Specifically, isolation regions are engineered with different metal compositions, thicknesses, or dielectric properties compared to contact regions, enabling selective electrical isolation where needed while maintaining low resistance where required.
3Ease of manufacture
If CMOS compatible metal is used for source and drain contacts, then manufacturing cost is reduced, but ohmic resistance increases
Solution Approach 1:
The patent employs composite contact structures consisting of multiple metal layers with complementary properties. For example, a stack of tungsten, cobalt, and nickel layers is used where each layer contributes different characteristics: one layer provides low resistance, another provides good adhesion, and another provides compatibility with subsequent processing. This composite approach achieves low ohmic resistance while using CMOS-compatible materials.
Solution Approach 2:
The patent performs preliminary annealing or surface treatment of the CMOS-compatible metal layers before final contact formation. This preliminary action prepares the metal surface to achieve lower resistance characteristics, ensuring that the final contact structure meets performance requirements despite using cheaper materials.
4Reliability
If direct alloying of metal with GaN/AlGaN is performed, then contact resistance is reduced, but the alloy layer is susceptible to removal by subsequent etching steps
Solution Approach 1:
The patent introduces an intermediate barrier layer or protective coating between the metal contact and the GaN/AlGaN semiconductor layer. This intermediary protects the alloy interface from being removed by subsequent etching steps while maintaining the low-resistance electrical contact, thereby resolving the stability issue without sacrificing contact performance.
Solution Approach 2:
The patent creates a composite contact structure where the alloyed metal layer is combined with more etch-resistant metal layers or protective dielectric layers. This composite structure maintains the beneficial low-resistance alloy interface while adding protective elements that prevent removal during subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces contact resistance to match or exceed the performance of Au-based technologies, enabling efficient and cost-effective fabrication of GaN-based HEMT devices on various substrates while minimizing photo-resist steps and preventing electrical shorts.
Implementation Method 1
annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination
Implementation Method 2
growing a first and a second nucleation layer on a substrate
Data Source
AI summary
There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.