GaN Semiconductor Device With Contact Layer For Withstand Voltage
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Solution Overview
Problem
Conventional semiconductor devices face challenges in enhancing withstand voltage, particularly when the gate is OFF, due to breakdown issues at corner portions of the gate trench portion, which can impair switching function and reliability.
Innovation Solution
The semiconductor device incorporates a contact layer with a higher second-conduction-type impurity concentration than the base region, epitaxially formed to contact the mesa region and isolation trench portions, and a source region with matching impurities, along with a specific structure to prevent punch-through and insulation breakdown, utilizing GaN-based semiconductor materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a gate trench portion is provided in a mesa region, then the device structure is improved for vertical integration, but breakdown occurs at corner portions of the gate trench when the gate is OFF
Solution Approach 1:
The patent applies local quality by providing a p+-type layer specifically at the corner portions of the gate trench portion, rather than uniformly throughout the entire device. This localized doping creates a high-concentration region exactly where the electrical field is most intense and breakdown is most likely to occur, thereby strengthening the薄弱环节 (weak link) without unnecessarily complicating the overall device structure.
Solution Approach 2:
The p+-type layer is formed in advance during the epitaxial growth process, before the device undergoes operation. This preliminary action of creating a protective high-concentration doping region preemptively counteracts the harmful electrical field concentration that would otherwise occur at the corner portions during OFF-state operation, preventing breakdown before it can happen.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively enhances the withstand voltage and reliability by preventing punch-through and insulation breakdown, ensuring stable operation even during the OFF period by managing the depletion layer expansion and electrical field distribution.
Implementation Method 1
managing the depletion layer expansion and electrical field distribution
Implementation Method 2
managing the depletion layer expansion and electrical field distribution
Implementation Method 3
epitaxially formed to contact the mesa region and isolation trench portions
Data Source
AI summary
Provided is a semiconductor device including at least two isolation trench portions; a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region.