GaN-on-Diamond Wafer Fabrication via Low-Temperature Bonding
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Solution Overview
Problem
Conventional GaN HEMT technology on SiC, sapphire, or Si substrates faces a thermal bottleneck due to poor thermal conductivity, leading to high device junction temperatures, mechanical stress, and reduced reliability, as heat generated from hotspots must traverse thick, low-conductivity GaN epitaxial layers before reaching the substrate.
Innovation Solution
A GaN on Diamond wafer is fabricated using a low-temperature bonding process that eliminates the nucleation layer, minimizes thermal expansion mismatch, and reduces GaN epitaxial layer thickness, allowing direct high-thermal-conductivity diamond substrate utilization, thereby improving thermal dissipation and mechanical stress management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high temperature direct CVD growth is used to bond GaN to diamond substrate, then strong bonding is achieved, but significant wafer bow and tensile stress occur due to CTE mismatch
Solution Approach 1:
The patent changes the bonding temperature parameter from high temperature (600-1000°C) to low temperature (below 400°C, preferably room temperature), which fundamentally alters the thermal expansion behavior and reduces CTE mismatch stress while achieving adequate bonding strength through surface preparation and bonding techniques
2Reliability
If thick GaN epitaxial layer is used, then device functionality is maintained, but thermal dissipation efficiency is reduced due to thermal barrier
Solution Approach 1:
The patent changes the GaN layer thickness parameter from thick (several micrometers) to thin (less than 1 micrometer, preferably 10-500 nanometers), which dramatically reduces thermal resistance while maintaining device functionality through optimized thin-film device design
3Ease of manufacture
If nucleation layer and buffer layers are included, then GaN growth is facilitated, but thermal conductivity is reduced due to additional thermal barriers
Solution Approach 1:
The patent extracts and removes the nucleation layer and buffer layers from the structure, eliminating these thermal barrier layers entirely while using alternative low-temperature bonding techniques that do not require these intermediate layers for successful GaN-diamond integration
4Loss of energy
If GaN layer is bonded to diamond substrate, then thermal dissipation is improved, but wafer bow occurs due to CTE mismatch
Solution Approach 1:
The patent changes the bonding temperature parameter to low temperature, which minimizes the differential thermal expansion between GaN and diamond during the bonding process and subsequent cooling, thereby reducing wafer bow while preserving the high thermal conductivity benefit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance and reliability by leveraging diamond's high thermal conductivity, reducing wafer bow, and minimizing stress, resulting in 3-5× higher power handling capability compared to GaN-on-SiC HEMT, enabling smaller, more efficient RF sources with reduced cooling and power requirements.
Implementation Method 1
mismatch in coefficient of thermal expansion (CTE) between GaN and diamond results in significant wafer bow as well as tensile stress in the GaN epitaxial layers
Implementation Method 2
diamond's high thermal conductivity
Data Source
AI summary
A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.