GaN Die Rearside Insulating Layer for Thermal Decoupling

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Solution Overview

Problem

Existing semiconductor devices, particularly Group III nitride devices like GaN HEMTs, face challenges in thermal management, leading to potential temperature rises and reduced performance in high-power applications.

Innovation Solution

The implementation of an electrically insulating inorganic layer on the rear side of the base substrate decouples the electrical and thermal paths, allowing for improved thermal cooling by reducing the thermal resistance and enabling direct contact with a heatsink.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If Group III nitride devices are used in high-power applications, then power handling capability is improved, but thermal management becomes problematic leading to temperature rises

Engineering Contradiction:
Improvepower handling capabilityVSAvoidtemperature rise
Core Design Contradiction:
PowerVSTemperature

Solution Approach 1:

The patent segments the thermal and electrical paths by introducing a separate thermal management structure. The semiconductor device is divided into functional regions where heat dissipation is handled independently from electrical operations, allowing high-power operation without proportional temperature increases.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary thermal management layer or structure between the heat-generating semiconductor device and the heat sink. This intermediary facilitates efficient heat transfer while maintaining electrical isolation, solving the thermal management problem in high-power applications.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If electrical and thermal paths are coupled, then device structure is simplified, but thermal cooling efficiency is reduced due to higher thermal resistance

Engineering Contradiction:
Improvedevice structureVSAvoidthermal resistance
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent segments the thermal and electrical pathways into separate channels. By providing dedicated thermal vias or heat transfer paths that are distinct from electrical interconnects, the design reduces thermal resistance without significantly increasing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent addresses thermal management by adding a vertical dimension to heat dissipation through thermal vias or under-battlement heat sinks. This three-dimensional thermal path reduces thermal resistance without complicating the planar device structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively alleviates thermal stress in semiconductor dies, enhancing their performance and reliability in high-power applications by ensuring efficient heat dissipation.

Implementation Method 1

The second metallization structure comprises an electrically insulating inorganic layer arranged directly on the second major surface... allowing for improved thermal cooling by reducing the thermal resistance

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentEP4495990A1Semiconductor substrate, semiconductor component and methods
Publication Date: 2025.01.22 INFINEON TECH AUSTRIA AG
  • EP4495990A1 patent drawingFigure 1A~1B
  • EP4495990A1 patent drawingFigure 2~3
  • EP4495990A1 patent drawingFigure 4

AI summary

In an embodiment, a semiconductor die comprises a base substrate comprising a first major surface and a second major surface opposing the first major surface, the base substrate comprising a material other than a Group III nitride, a Group III nitride layer arranged on the first major surface of the base substrate, the Group III nitride layer comprising a Group III nitride device, a first metallization structure arranged on the Group III nitride layer and a second metallization structure arranged on the second major surface of the base layer. The second metallization structure comprises an electrically insulating inorganic layer arranged directly on the second major surface.