GaN Doherty Power Amplifier Layout for Uniform FET Cell Loading
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Solution Overview
Problem
Gallium nitride (GaN) power amplifiers face inefficiencies in power scaling, where increasing the number of FET cells does not proportionally increase output power, leading to reduced power efficiency, particularly due to uneven power distribution and impedance imbalances across FET cells.
Innovation Solution
The power amplifier design features FET cells at opposing ends with larger total gate width and reduced inductance, while center cells have reduced gate width and increased inductance, to minimize impedance differences and enhance power distribution, maintaining a consistent total gate width and inductance across the row of FET cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of FET cells is increased to scale up power output, then the total power output increases, but the power efficiency decreases due to uneven power distribution and impedance imbalances
Solution Approach 1:
The patent applies local quality by varying the gate width of individual FET cells based on their position in the array. Center cells have reduced gate width while outer cells have increased gate width, creating non-uniform local characteristics that compensate for impedance imbalances and achieve more uniform power distribution across all cells, thereby maintaining high power efficiency at scaled-up power levels
Solution Approach 2:
The patent changes the gate width parameter of FET cells according to their position in the array. By systematically adjusting this critical parameter - reducing it for center cells and increasing it for outer cells - the invention optimizes power distribution and eliminates the efficiency degradation that normally occurs when scaling up power output through simple cell multiplication
2Ease of manufacture
If uniform gate width is used across all FET cells, then manufacturing is simplified, but impedance imbalances cause uneven power distribution reducing overall efficiency
Solution Approach 1:
The patent implements local quality by assigning different gate widths to FET cells based on their position - outer cells have larger gate widths while center cells have smaller gate widths. This localized variation compensates for impedance imbalances inherent in large-scale FET arrays, achieving uniform power distribution and high efficiency while remaining compatible with standard manufacturing processes
Solution Approach 2:
The patent applies asymmetry by deliberately creating non-uniform gate width distribution across the FET cell array. Instead of symmetric uniform sizing, the design uses asymmetric sizing patterns (larger outer cells, smaller center cells) to counteract the symmetric impedance imbalances that naturally occur in expanded FET configurations, thereby optimizing power efficiency
3Device complexity
If FET cells are arranged in a row with standard configuration, then device complexity is low, but impedance differences between cells cause reduced power added efficiency
Solution Approach 1:
The patent changes the gate width parameter of FET cells based on their position in the row configuration. By systematically varying this parameter - reducing gate width for center cells and increasing it for outer cells - the invention optimizes impedance matching and power distribution across the linear array, achieving high power added efficiency while maintaining the simple row-based device layout
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves power added efficiency and increases saturated power output, as demonstrated by enhanced power added efficiency from 65.1% to 72% in comparison with standard designs.
Implementation Method 1
The one or more first output bondwires 52 at least partially form, for said FET cell, a first inductor between the drain base Bd of that FET cell and the first terminal 51 of the output capacitive element
Data Source
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AI summary
The present invention relates to a power amplifier and to a Doherty amplifier comprising the same. The present invention particularly relates to gallium nitride, GaN, power amplifiers operating at radiofrequency, RF, frequencies. According to the present invention, the power amplifier comprises one or more RF output terminals, a Gallium Nitride, GaN, semiconductor die on which a power field-effect transistor, FET, is integrated, wherein the FET comprises a plurality of FET cells that are adjacently arranged in a row, wherein the FET cells are connected to the one or more RF output terminals either directly or indirectly via a respective first inductor. According to the present invention, for FET cells arranged at opposing ends of the row of FET cells, a total FET cell gate width and an inductance of the first inductor is larger and smaller than the total FET cell gate width and inductance of the first inductor for one or more FET cells arranged in the middle of the row of FET cells, respectively.