GaN Transistor Lateral Drain Depletion for Lower Parasitic Capacitance
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Solution Overview
Problem
Current GaN-on-Si transistors face challenges in achieving high RF performance comparable to III-V or SiGe technologies due to limitations in power gain and efficiency, particularly at high frequency bands, and require improvements in parasitic capacitance and breakdown voltage to meet the demands of advanced compute solutions.
Innovation Solution
The implementation of source field-plates in GaN transistors to create a laterally depleted drain region, minimizing parasitic capacitance and enhancing breakdown voltage, along with multi-gate structures and heterostructures, enables improved RF performance and power delivery efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GaN-on-Si transistor structures are used, then manufacturing simplicity is maintained, but RF performance and power gain are insufficient at high frequency bands
Solution Approach 1:
The transistor structure is segmented into multiple gates (first gate and second gate) with different threshold voltages, allowing independent control of different channel regions. This segmentation enables optimized RF performance by controlling carrier flow in specific regions while maintaining manufacturability through modular device architecture.
Solution Approach 2:
Different regions of the transistor are given different local properties through varying polarization layer thicknesses beneath each gate. The first gate region has a thinner polarization layer for lower threshold voltage and higher current drive, while the second gate region has a thicker polarization layer for higher threshold voltage and better off-state control, optimizing overall RF performance.
2Strength
If standard gate structures are used, then device simplicity is maintained, but parasitic capacitance is high and breakdown voltage is insufficient
Solution Approach 1:
The transistor transitions from a planar single-gate structure to a multi-gate configuration where gates are arranged in different spatial dimensions. This dimensional change allows for better electric field control and higher breakdown voltage while the different threshold voltages enable independent optimization of various performance parameters.
3Power
If uniform polarization layer thickness is used, then manufacturing simplicity is maintained, but power gain and efficiency are insufficient
Solution Approach 1:
The polarization layer thickness is varied locally beneath different gate regions to create distinct threshold voltages. This local variation enables optimized power gain by controlling carrier distribution and current flow in different channel regions, while the heterostructure approach maintains compatibility with existing GaN-on-Si manufacturing processes.
Data Source
AI summary
Gallium nitride (GaN) transistors with lateral depletion for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen above a silicon substrate, a gate structure over the layer including gallium and nitrogen, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, and a source field plate laterally between the gate structure and the drain region, the source field plate laterally separated from the gate structure.