GaN E-HEMT Interface Layer Grading for Better Gate Control

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Solution Overview

Problem

Silicon-based semiconductor devices face limitations in achieving higher current, voltage, and power density while maintaining energy efficiency, particularly due to issues with gate control and reliability in high-power and high-frequency applications, where wide band gap semiconductors like GaN-based E-HEMTs are needed to enhance performance.

Innovation Solution

A doped interface layer with a graded metal concentration, specifically aluminum, is introduced between the barrier layer and the doped layer in a semiconductor structure to reduce the presence of two-dimensional electron hole gas (2DHG) above the Fermi level, improving gate control and device reliability by minimizing lattice mismatch and interface trapping centers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional doped layer is formed directly on the barrier layer, then the device structure is simple, but interface trapping centers increase and gate control deteriorates

Engineering Contradiction:
Improvegate controlVSAvoidlayer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A doped interface layer is introduced between the barrier layer and the doped layer to act as an intermediary structure. This interface layer has a graded composition that transitions from the barrier layer material to the doped layer material, reducing interface trapping centers and improving gate control without excessive structural complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The doped interface layer has a graded composition where the concentration of group III elements varies through the layer thickness. This local variation in composition optimizes the interface properties locally, reducing trapping centers at the critical interface regions while maintaining overall device performance

Inventive Principle:
Principle #3Local quality

2Power

If high current and power density are achieved in silicon-based devices, then power handling capability increases, but energy efficiency and reliability deteriorate due to gate control issues

Engineering Contradiction:
Improvepower densityVSAvoiddevice reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The invention changes the compositional parameters of the interface layer by using a graded concentration of group III elements. This parameter gradient optimizes the electrical properties at the interface, enabling higher power density operation while maintaining reliability through improved gate control and reduced interface trapping

Inventive Principle:
Principle #35Parameter changes

3Reliability

If aluminum concentration is increased in the barrier layer, then Schottky barrier height increases for better rectification, but lattice mismatch increases causing more interface defects

Engineering Contradiction:
Improverectification performanceVSAvoidlattice matching
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The doped interface layer implements a local quality transition by gradually changing the group III element composition from the barrier layer to the doped layer. This graded composition locally accommodates the lattice mismatch caused by high aluminum concentration in the barrier layer, reducing interface defects while maintaining the high Schottky barrier height for rectification

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention uses parameter changes in the form of a compositional gradient through the doped interface layer. The group III element concentration varies continuously from the barrier layer side to the doped layer side, providing a transition that reduces lattice mismatch effects while allowing the barrier layer to maintain high aluminum concentration for optimal rectification

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240079486A1Semiconductor structure and method of manufacture
Publication Date: 2024.03.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240079486A1 patent drawing
  • US20240079486A1 patent drawing
  • US20240079486A1 patent drawing

AI summary

A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.