GaN Vertical Devices Using Engineered Substrates
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Solution Overview
Problem
Conventional power electronics face challenges in fabricating high-performance vertical GaN-based devices due to substrate limitations, such as high substrate resistance and defect densities when using foreign substrates like silicon carbide, which restricts device thickness and introduces defects.
Innovation Solution
The use of engineered substrates with III-nitride seed layers and homoepitaxial GaN layers allows for the fabrication of vertical GaN-based devices, reducing substrate resistance and defect density, and enabling the growth of high-quality GaN epitaxial layers with improved electron mobility and critical electric field, thus enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If foreign substrates like silicon carbide are used for GaN-based devices, then device fabrication is enabled, but substrate resistance increases and defect density increases
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the foreign substrate and the GaN-based functional layers. This buffer layer mediates the interface between mismatched materials, reducing defect propagation and lowering substrate resistance while enabling successful device fabrication on foreign substrates.
Solution Approach 2:
The patent modifies substrate parameters by using engineered substrates with specific properties (such as matched thermal expansion coefficients and lattice constants) and controlling buffer layer thickness and composition. These parameter changes optimize the interface quality, reducing both substrate resistance and defect density while maintaining manufacturability.
2Ease of manufacture
If foreign substrates like silicon carbide are used for GaN-based devices, then device fabrication is enabled, but defect density increases
Solution Approach 1:
The buffer layer serves as a mediator that isolates the GaN-based functional layers from the foreign substrate, preventing defect propagation from the substrate interface. This intermediary layer enables fabrication on foreign substrates while maintaining low defect densities in the active device regions.
Solution Approach 2:
The patent applies local quality by creating a buffer layer with specific properties at the substrate interface, while the GaN-based functional layers above maintain different, optimized properties. This localized structural differentiation allows the interface region to handle the mismatch while the active regions maintain high quality with low defect density.
3Reliability
If substrate thinning/removal is performed to reduce resistance, then substrate resistance decreases, but processing complexity increases
Solution Approach 1:
The patent performs substrate thinning and buffer layer removal as preliminary actions during the fabrication process, before final device assembly. By completing these resistance-reducing steps early, the patent simplifies subsequent processing while achieving the desired low substrate resistance in the final device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower substrate resistance, reduced processing costs, and improved thermal conductivity, enabling the creation of high-power, low-resistance GaN-based devices with superior reliability and performance characteristics, such as normally-off vertical JFETs with optimized dopant concentrations.
Implementation Method 1
providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer
Data Source
AI summary
A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.