GaN Epitaxial Structure Using Dislocation Pits to Bend Defects
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Solution Overview
Problem
The current manufacturing of GaN-based optoelectronic and power devices faces challenges due to thermal and lattice mismatch between the GaN epitaxial layer and substrates, leading to dislocation issues, decreased uniformity, and increased costs.
Innovation Solution
An epitaxial structure is developed with a substrate and an epitaxial layer comprising a first sub-epitaxial layer group, where the second sub-epitaxial layer covers dislocation pits on the first sub-epitaxial layer, causing dislocations to bend and reducing their upward extension, thereby improving uniformity and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional substrates (SiC, Si, sapphire) are used for GaN epitaxial growth, then manufacturing cost is reduced and ease of manufacture is improved, but thermal mismatch and lattice mismatch generate significant dislocations and deformation, worsening epitaxial layer uniformity and product yield
Solution Approach 1:
The patent introduces an intermediary buffer structure between the conventional substrate and the GaN epitaxial layer. This buffer layer acts as a mediator that gradually transitions from the substrate's crystal structure to the GaN crystal structure, reducing the abrupt mismatch. The buffer layer absorbs thermal and lattice mismatch stresses while preventing dislocation propagation into the GaN layer, thereby maintaining both ease of manufacture on conventional substrates and high epitaxial layer uniformity.
Solution Approach 2:
The patent employs parameter changes by gradually varying the composition and thickness of buffer layers during the epitaxial growth process. By controlling parameters such as aluminum content in AlN buffer layers, growth temperature, and layer thickness sequences, the patent optimizes the transition from substrate to GaN layer. This gradual parameter change reduces thermal stress accumulation and lattice mismatch, improving epitaxial layer uniformity while maintaining compatibility with conventional substrates.
2Manufacturing precision
If process conditions are optimized to improve GaN crystal quality, then dislocation density is reduced, but leakage problems occur and the extent of improvement is limited
Solution Approach 1:
The patent applies local quality by creating regions with different compositions and properties within the buffer structure. Specific buffer layers have tailored aluminum content and thickness to address local stress concentrations and dislocation sources. This localized optimization allows different parts of the buffer structure to perform different functions: some layers focus on reducing dislocation density while others prevent leakage paths, thereby simultaneously improving crystal quality and reliability without the trade-off present in conventional uniform buffer designs.
3Manufacturing precision
If GaN homoepitaxial substrates are used to enhance crystal quality, then dislocation density is significantly reduced, but the inherent physical property limitations make bulk single crystal growth very difficult and impractical
Solution Approach 1:
The patent segments the epitaxial structure into multiple functional layers: conventional substrate, nucleation layer, buffer layers with varying compositions, and GaN epitaxial layers. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall manufacturability. The buffer layers are divided into multiple sub-layers with gradient compositions, enabling gradual crystal structure transition without requiring difficult-to-manufacture bulk GaN substrates, thus achieving high crystal quality through a manufacturable segmented structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances epitaxial layer uniformity, improves crystal quality, and reduces costs by effectively managing dislocations and optimizing the growth process.
Implementation Method 1
an epitaxial layer located on one side of the substrate, the epitaxial layer comprising at least a first sub-epitaxial layer group, the first sub-epitaxial layer group comprising a first sub-epitaxial layer and a second sub-epitaxial layer arranged in stack, the second sub-epitaxial layer being located on one side of the first sub-epitaxial layer away from the substrate
Data Source
AI summary
Embodiments of the present invention relate to an epitaxial structure of a semiconductor device and a manufacturing method thereof, and a semiconductor device. The epitaxial structure of the semiconductor device comprises: a substrate; and an epitaxial layer located on one side of the substrate, the epitaxial layer comprising at least a first sub-epitaxial layer group, the first sub-epitaxial layer group comprising a first sub-epitaxial layer and a second sub-epitaxial layer arranged in stack; wherein, a surface of one side of the first sub-epitaxial layer away from the substrate comprises a plurality of first dislocation pits, and sidewalls of the first dislocation pits intersect both a plane where the first sub-epitaxial layer is located and a first direction; and the second sub-epitaxial layer covers at least the sidewalls of the first dislocation pits. In the embodiments of the present invention, most of the dislocations in the second sub-epitaxial layer that originally extended upward along the first direction will change their extension direction at the first dislocation pit, and the dislocations bend, thereby reducing most of the dislocations extending upward along the first direction, improving the uniformity of the epitaxial layer, improving crystal quality and product yield, and reducing costs.