GaN Integrated Circuit Epitaxy for Low-Dislocation Buffer Layers
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Solution Overview
Problem
Current integrated circuits fabricated using heteroepitaxial growth on metal organic chemical vapor deposition (MOCVD) methods face challenges in achieving high performance and reliability due to high dislocation density and lattice mismatch issues, particularly when grown on substrates like SiC and Si, leading to defects and reduced crystalline quality.
Innovation Solution
The integration of a substrate with a first nucleation layer, a buffer layer, and a channel layer, where the first nucleation layer is fabricated using Physical Vapor Deposition (PVD) or Pulsed Laser Deposition (PLD) processes, reducing substrate quality requirements and allowing for epitaxial growth of high-quality GaN on substrates with large lattice mismatches, and the use of doped GaN or AlGaN buffer layers with optimized Sc or In atomic percentages to minimize lattice mismatch and dislocation density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heteroepitaxial growth is performed on substrates with large lattice mismatches (such as SiC and Si) using conventional MOCVD methods, then substrate compatibility and manufacturing versatility are improved, but dislocation density increases and crystalline quality deteriorates
Solution Approach 1:
The patent segments the epitaxial growth process into multiple stages with different buffer layer compositions. The buffer layer transitions from GaN to AlGaN with varying Al content, creating intermediate steps that progressively accommodate the lattice mismatch between the substrate and the final GaN layer, thereby reducing dislocation density while maintaining substrate compatibility
Solution Approach 2:
The patent changes the compositional parameter of the buffer layer by incorporating AlGaN with different Al content ratios. This parameter adjustment allows the buffer layer to serve as a transition medium that bridges the lattice constant difference between substrates (SiC, Si) and GaN, reducing dislocation formation while enabling growth on diverse substrates
2Ease of manufacture
If conventional buffer layers are used in heteroepitaxial growth, then manufacturing process simplicity is maintained, but dislocation density remains high and device reliability deteriorates
Solution Approach 1:
The patent employs composite buffer layer structures combining GaN and AlGaN layers with optimized thicknesses and compositions. This composite approach creates a gradient that effectively manages dislocation propagation while remaining compatible with existing MOCVD manufacturing processes, thereby improving device reliability without significantly complicating the manufacturing workflow
3Productivity
If epitaxial growth is performed on large substrates, then production capacity and device area are improved, but maintaining uniform crystalline quality across the substrate becomes more difficult
Solution Approach 1:
The patent implements buffer layers with spatially varying compositions optimized for different regions of the substrate. By adjusting Al content and layer thickness locally, the buffer structure adapts to variations in temperature and stress across large substrates, ensuring uniform crystalline quality and low dislocation density throughout the entire device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves crystalline quality and epitaxial growth, enhancing device performance and long-term reliability by reducing dislocation density and lattice mismatch, enabling high-quality GaN growth on substrates with large lattice mismatches, such as SiC and Si, and supporting larger substrate sizes.
Implementation Method 1
the first nucleation layer is fabricated using Physical Vapor Deposition (PVD) or Pulsed Laser Deposition (PLD) processes
Implementation Method 2
the first nucleation layer is fabricated using Physical Vapor Deposition (PVD) or Pulsed Laser Deposition (PLD) processes
Implementation Method 3
allowing for epitaxial growth of high-quality GaN on substrates with large lattice mismatches
Data Source
AI summary
An integrated circuit, a manufacturing method thereof, a power amplifier, and an electronic device are provided. The integrated circuit includes: a substrate (1), a first nucleation layer (2) located on the substrate (1), a buffer layer (3) located on the first nucleation layer (2), a channel layer (4) located on the buffer layer (3), a barrier layer (5) located on the channel layer (4), and a source (6), a drain (7), and a gate (8) that are separately located on the barrier layer (5). A dislocation density of the buffer layer (3) is less than 1e8 cm−2, so that crystalline quality can be improved, and a higher-quality epitaxial growth material can be obtained, to improve device performance and long-term reliability of the integrated circuit.