Conformal P-Type GaN Epitaxy Over Thick Buffer Layers
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Solution Overview
Problem
Gallium nitride field effect transistors (GaN FETs) operating above several hundred volts face challenges in achieving optimal performance due to the thickness and structural variations of the buffer layer on silicon substrates, which affect the isolation and uniformity of the device.
Innovation Solution
A semiconductor device with a buffer layer comprising a columnar region, transition region, and inter-columnar region on a silicon substrate, where the columnar region has a higher lateral width and a more constant thickness, and the transition region has a sloping top surface, along with a barrier layer and gate layer formed using MOVPE processes to enhance the device's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick buffer layer is used to isolate the GaN FET from the silicon substrate for high voltage operation, then the isolation and voltage handling capability are improved, but the structural uniformity and thickness consistency deteriorate
Solution Approach 1:
The buffer layer is divided into multiple sublayers with different compositions and thicknesses: a first buffer layer (30-100 nm) with higher aluminum content, a second buffer layer (100-500 nm) with intermediate aluminum content, and a third buffer layer (500 nm-5 µm) with lower aluminum content. This segmentation allows each sublayer to serve specific functions while collectively achieving both thick-layer isolation and uniform thickness control.
Solution Approach 2:
Different regions of the buffer layer structure have different aluminum contents tailored to specific locations: the first buffer layer near the substrate has higher aluminum for lattice matching and defect reduction, while the third buffer layer closer to the GaN layer has lower aluminum for better lattice matching with GaN. This local quality variation enables simultaneous achievement of thick buffer isolation and uniform thickness.
2Reliability
If the buffer layer thickness is increased to several microns for high voltage operation, then the voltage handling capability is improved, but the device uniformity and performance consistency worsen
Solution Approach 1:
The thick buffer layer is segmented into three distinct sublayers, each with controlled thickness and aluminum content. This segmentation prevents the formation of large thickness variations that would occur in a single uniform thick layer, while still achieving the required several-micron total thickness for high voltage operation.
Solution Approach 2:
The aluminum content parameter is systematically changed across the buffer layer structure: the first buffer layer has higher aluminum content (closer to AlN stoichiometry), the second has intermediate content, and the third has lower content (closer to GaN stoichiometry). This parameter gradient enables the thick buffer layer to maintain uniform composition and structure throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described structure and fabrication process improve the uniformity and performance of GaN FETs by maintaining a consistent thickness and reducing defects, leading to better isolation and operational efficiency at high voltages.
Implementation Method 1
forming the barrier layer over the top surface by a barrier MOVPE process. A gate layer is formed of III-N semiconductor material over the barrier layer by a gate MOVPE process
Data Source
AI summary
A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.