GaN ESD Protection Circuit With Dual Triggered Discharge Paths
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Solution Overview
Problem
Gallium nitride (GaN) based devices are prone to damage from electrostatic discharge due to their low gate breakdown voltage, which can be exceeded by voltage overshoot during switching or discharge events, leading to potential gate terminal damage.
Innovation Solution
An electrostatic discharge (ESD) protection circuit is integrated into the IC chip, comprising two sub-circuits with different trigger voltages, where GaN based transistors are connected in series or parallel configurations to provide robust protection by channeling electrostatic discharge surges without increasing transistor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GaN based devices are used for high-frequency and high-power applications, then productivity and power efficiency are improved, but the gate becomes vulnerable to electrostatic discharge damage due to low breakdown voltage
Solution Approach 1:
The patent introduces an ESD protection circuit as an intermediary component between the external environment and the GaN HEMT gate terminal. This protection circuit includes trigger circuits and discharge components that detect voltage overshoot conditions and provide a controlled discharge path, thereby protecting the gate terminal from electrostatic discharge damage while allowing the GaN device to maintain its high-frequency and high-power performance capabilities
2Reliability
If ESD protection circuit is added to protect GaN HEMT, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the ESD protection functionality with the existing GaN HEMT circuit structure by integrating trigger circuits and discharge components that work in conjunction with the HEMT's existing terminals (gate, drain, source). The protection circuit shares voltage dividers and trigger nodes with the main device, thereby providing comprehensive ESD protection while minimizing the increase in overall device complexity
Solution Approach 2:
The ESD protection circuit is segmented into distinct functional modules: voltage divider circuits for detection, trigger circuits for activation, and discharge components for current routing. This segmentation allows each module to be optimized independently and facilitates integration with the GaN HEMT structure while maintaining clear functional separation and reducing overall system complexity
3Reliability
If larger current passage capability is provided during ESD events, then protection effectiveness is improved, but transistor area increases
Solution Approach 1:
The patent utilizes the voltage dimension by implementing voltage divider circuits that detect voltage overshoot conditions. By monitoring the voltage across the gate terminal and comparing it against threshold values, the protection circuit can activate discharge paths selectively based on voltage levels rather than requiring continuously large current handling capability across all operating conditions
Solution Approach 2:
The discharge components in the protection circuit are designed to dynamically adjust their current handling capability based on the detected ESD event severity. During normal operation, the circuit maintains low impedance paths for signal integrity, but during ESD events, the trigger circuits activate to provide low-impedance discharge paths that can handle large currents temporarily, thereby providing effective protection without requiring permanently large transistor areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ESD protection circuit effectively prevents GaN based HEMT damage by allowing larger current passage during electrostatic discharge events, ensuring reliable operation without unnecessary chip size expansion.
Implementation Method 1
Electrostatic discharge is a sudden release of electrostatic charges, which may result in a high electric field and current within the integrated circuit (IC), thereby damaging the GaN based device therewithin
Data Source
AI summary
The present disclosure provides an ESD protection circuit coupled between first and second reference terminals. The ESD protection circuit includes first and second voltage dividers, first and second trigger circuits, and first and second discharge components. The first trigger circuit and the first voltage divider are coupled in series. The second voltage divider and the second trigger circuit are coupled in series. A gate of the first discharge component is coupled between the first trigger circuit and the first voltage divider. A gate of the second discharge component is coupled between the second trigger circuit and the second voltage divider. The second trigger circuit includes a first GaN based transistor, which comprises a first source/drain, a second source/drain and a gate. The first source/drain and the second source/drain are coupled to the second reference terminal. The gate is coupled to the second voltage divider.