GaN Transistor ESD Protection Circuit Design

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Solution Overview

Problem

Group III-V compound-based transistors, such as GaN-based HEMTs, are susceptible to electrostatic discharge (ESD) events due to their low gate breakdown voltage, leading to potential damage from voltage overshoot spikes, and require an effective ESD protection circuit to prevent electrostatic breakdown.

Innovation Solution

The implementation of a specifically designed ESD protection circuit comprising GaN-based transistors and diodes connected in series, with resistors, to discharge accumulated charge and prevent gate oxide breakdown, ensuring the transistor operates safely during ESD events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If GaN-based transistors are used to achieve high-speed operation and high breakdown voltage, then device performance is improved, but susceptibility to ESD events increases due to low gate breakdown voltage

Engineering Contradiction:
Improvebreakdown voltageVSAvoidESD resistance
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent introduces an ESD protection circuit as an intermediary component between the signal source and the GaN transistor gate. This protection circuit includes protective elements (such as diodes or transistors) that act as mediators to intercept and divert ESD current away from the vulnerable gate oxide, thereby protecting the high-performance GaN transistor from damage while maintaining its high breakdown voltage capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the protection function from the main transistor operation by adding a separate ESD protection circuit. This segmentation allows the GaN transistor to maintain its high-power characteristics while the separate protection circuit handles ESD events, resolving the contradiction between performance and ESD resistance

Inventive Principle:
Principle #1Segmentation

2Reliability

If an ESD protection circuit is added to protect against ESD events, then reliability is improved, but device complexity increases

Engineering Contradiction:
ImproveESD protectionVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the ESD protection function with the existing transistor structure by integrating protective elements (such as diodes connected to gate and source/drain) into the device architecture. This combining approach provides ESD protection while minimizing the increase in overall device complexity compared to completely separate protection circuits

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The ESD protection circuit is designed to automatically activate during ESD events without external control, using the voltage spike itself to trigger the protective mechanism. This self-service approach simplifies the control logic and reduces complexity while maintaining reliable protection

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11715946B2Electronic device and electrostatic discharge protection circuit
Publication Date: 2023.08.01 INNOSCIENCE (SUZHOU) SEMICON CO LTD
  • US11715946B2 patent drawing
  • US11715946B2 patent drawing
  • US11715946B2 patent drawing

AI summary

An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.