Normally-off GaN FET with Bottom Barrier Gate

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Solution Overview

Problem

High-power field-effect transistors like GaN-based HFETs are typically normally-on devices, which are not suitable for power electronics due to potential gate voltage source failures leading to high currents and damage, and existing solutions for achieving normally-off operation result in performance degradation such as excessive leakage currents and lower breakdown voltage.

Innovation Solution

A field-effect transistor design featuring a barrier above the channel and an additional barrier layer below it, where the bandgap of each barrier is larger than the channel's, inducing polarization charge for depletion and allowing voltage-controlled on-state operation, with the bottom barrier acting as a gate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a GaN-based HFET is designed as a normally-on device, then high power and breakdown voltage are achieved, but the device is unsuitable for power electronics due to gate voltage source failures causing high currents and damage

Engineering Contradiction:
Improvehigh powerVSAvoidsafety against gate voltage failure
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent inverts the conventional approach by designing a normally-off device instead of a normally-on device. This is achieved by introducing a p-type barrier layer at the AlGaN/GaN interface, which creates a depletion region that blocks current flow in the absence of gate voltage. The device only conducts when a sufficient gate voltage is applied to overcome the polarization-induced depletion, thereby ensuring safety against gate voltage failures while maintaining high power capability.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the electrical parameters of the device by introducing a p-type barrier layer with specific doping concentrations (1×10^16 to 1×10^18 atoms/cm³) and thickness (50 nm to 5 μm). This modification alters the device's default state from normally-on to normally-off by creating a controlled depletion region through polarization effects, while preserving the high breakdown voltage and power handling capabilities through careful parameter selection.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If etching is used to achieve normally-off condition, then normally-off operation is achieved, but performance degrades with excessive leakage currents and lower breakdown voltage

Engineering Contradiction:
Improvenormally-off operationVSAvoidbreakdown voltage
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

Instead of physically removing material through etching, the patent changes the electrical parameters by introducing a p-type barrier layer with controlled doping concentration (1×10^16 to 1×10^18 atoms/cm³) and thickness (50 nm to 5 μm). This approach achieves normally-off operation through polarization-induced depletion while maintaining high breakdown voltage by avoiding the physical damage and performance degradation associated with etching processes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure combining p-type AlGaN barrier layer with n-type GaN channel layer. This composite material approach creates a heterostructure that utilizes polarization effects at the interface to achieve normally-off operation without the performance penalties of conventional etching methods, preserving both high breakdown voltage and low leakage current characteristics.

Inventive Principle:
Principle #40Composite materials

3Reliability

If cascade connections with silicon devices are used, then normally-off operation is achieved, but parasitic parameters and series resistance increase

Engineering Contradiction:
Improvenormally-off operationVSAvoidparasitic parameters
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the normally-off functionality directly into the GaN HFET structure by integrating a p-type barrier layer within the device architecture. This eliminates the need for external cascade connections with silicon devices, thereby reducing parasitic parameters and series resistance while achieving normally-off operation. The combined structure operates as a single unified device rather than a complex cascade connection.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts the normally-off control mechanism from external silicon-based cascade circuits and integrates it directly into the GaN HFET structure through the p-type barrier layer. This extraction eliminates the need for separate control devices and their associated parasitic elements, simplifying the overall device structure while maintaining normally-off operation.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables high operating voltage in a normally-off state with reduced leakage currents and improved breakdown voltage, enhancing reliability for power electronics applications.

Implementation Method 1

A polarization charge induced at the interface between the first barrier and the channel depletes the channel

Methodology Applied
Scientific EffectPolarization charge: Polarisation

Implementation Method 2

A voltage can be applied to the bottom barrier to induce free carriers into the channel, thus turning the channel on

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9887267B2Normally-off field effect transistor
Publication Date: 2018.02.06 SENSOR ELECTRONIC TECHNOLOGY INC
  • US9887267B2 patent drawing
  • US9887267B2 patent drawing
  • US9887267B2 patent drawing

AI summary

A normally-off transistor with a high operating voltage is provided. The transistor can include a barrier above the channel and an additional barrier layer located below the channel. A source electrode and a drain electrode are connected to the channel and a gate electrode is connected to the additional barrier layer located below the channel. The bandgap for each of the barrier layers can be larger than the bandgap for the channel. A polarization charge induced at the interface between the additional barrier layer below the channel and the channel depletes the channel. A voltage can be applied to the bottom barrier to induce free carriers into the channel and turn the channel on.