GaN Enhancement-Mode FET with Buried P-Type Threshold Control
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Solution Overview
Problem
Existing gallium nitride (GaN) semiconductor devices are typically depletion mode, which requires additional circuit complexity and is not suitable for high-frequency and high-power switching applications that require normally off switching elements.
Innovation Solution
The development of enhancement mode GaN semiconductor devices with a buried p-type region under the two-dimensional electron gas (2DEG) region, allowing for normally off operation with reduced circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If depletion mode GaN devices are used, then high breakdown electric field and high electron mobility are achieved, but circuit complexity increases and normally off switching is not available
Solution Approach 1:
The patent applies local quality by creating a p-type buried layer at a specific depth (50-200 nm) beneath the 2DEG channel, while leaving other regions with their original properties. This localized modification enables enhancement mode operation in the bulk region without affecting the high electron mobility of the 2DEG channel, thus achieving normally off switching while preserving the high breakdown electric field characteristics of GaN devices.
Solution Approach 2:
The patent transitions from a two-dimensional surface doping approach to a three-dimensional buried layer structure. By placing the p-type layer at a specific depth beneath the channel interface, the invention creates a vertical dimension control mechanism that enables enhancement mode operation while maintaining the lateral high electron mobility of the 2DEG, thereby reducing circuit complexity requirements.
2Speed
If depletion mode GaN devices are used, then high electron mobility is achieved, but normally off switching capability is lost
Solution Approach 1:
The p-type buried layer is introduced at a specific depth (50-200 nm) beneath the 2DEG channel, creating a localized region that controls the normally off switching capability. This localized modification allows the device to be normally off while preserving the high electron mobility in the channel region, enabling both enhancement mode operation and high-speed performance.
Solution Approach 2:
The p-type buried layer is pre-formed during the growth process before device fabrication, establishing the enhancement mode characteristics in advance. This preliminary action ensures that the device is normally off before any additional processing, simplifying the overall device operation and maintaining high electron mobility throughout the fabrication process.
3Ease of operation
If p-type material is introduced to create enhancement mode operation, then normally off switching is achieved, but device structure complexity increases
Solution Approach 1:
The patent resolves structure complexity by moving the p-type doping from the surface level to a buried depth of 50-200 nm beneath the channel. This vertical positioning eliminates the need for complex surface patterning and multiple doping steps, as the buried layer can be formed in a single growth process, thereby achieving enhancement mode operation with minimal structural complexity.
Solution Approach 2:
The p-type buried layer is incorporated during the initial epitaxial growth process, before any device-specific patterning or fabrication steps. This preliminary formation of the enhancement mode structure simplifies subsequent processing and reduces overall device structural complexity while maintaining normally off switching capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhancement mode GaN devices enable efficient high-power and high-frequency switching with reduced circuit complexity, making them suitable for high-power applications while minimizing costs.
Implementation Method 1
The enhancement mode device can include a layer of p-type GaN-based compound semiconductor material disposed on a region of aluminum nitride material under a 2DEG region formed by a GaN-based heterostructure. The layer of p-type material or the region of AlN material can be configured to deplete the 2DEG region when the enhancement mode device is unbiased.
Data Source
AI summary
An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.