GaN FET Defect Mitigation Structures for Short Gate Fabrication
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Solution Overview
Problem
Fabricating high-power field effect transistors (FETs) with short gate lengths using gallium nitride (GaN) on silicon carbide (SiC) substrates is challenging due to transparency issues and non-uniform flatness, and defects in ohmic contact structures can migrate, affecting device performance and reliability.
Innovation Solution
Incorporating a protective dielectric layer over ohmic contact structures and forming dielectric spacer structures to mitigate defects, allowing for shorter gate lengths and improved linearity performance by adjusting the gate length through dielectric spacer structures and a thin dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If photolithography alone is used to fabricate FETs with short gate lengths, then manufacturing process simplicity is maintained, but manufacturing precision deteriorates due to transparency of SiC substrates and non-uniform flatness of GaN-on-SiC substrates
Solution Approach 1:
A dielectric layer is formed over the substrate before photolithography to pre-establish a protective and planarizing structure. This preliminary action compensates for substrate non-uniformity and enables precise gate length fabrication that would otherwise be unachievable with photolithography alone on GaN-on-SiC substrates
2Ease of manufacture
If ohmic contact structures are formed without protective layers, then ease of manufacture is improved, but reliability deteriorates due to defect migration to the gate channel region
Solution Approach 1:
A dielectric layer is introduced as an intermediary barrier between the ohmic contact structures and the gate channel region. This intermediary prevents defect migration from the ohmic contacts to the gate channel, thereby improving device reliability while maintaining manufacturing simplicity
Solution Approach 2:
The dielectric layer is formed in advance to prevent the harmful effect of defect migration before it can occur. By establishing this protective barrier beforehand, the patent prevents reliability issues that would otherwise arise from ohmic contact defects migrating to the gate channel
Data Source
AI summary
A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. When fabricating the transistor device, at least one dielectric layer may be formed over ohmic contact structures of the transistor device, which may mitigate migration of material, such as metal, from the ohmic contact structures onto sensitive surfaces of the transistor device during subsequent fabrication processes. The transistor device may include one or more dielectric spacers, including at least one dielectric spacer disposed at a side wall of a gate channel through which gate structure contacts the substrate. The transistor device may include a field plate formed at least partially over the gate structure, the field plate having one or more stepped portions, which may improve linearity performance of the transistor device.