GaN FET Gate Metal Overhang and Via Distribution
Solution Overview
Problem
Existing GaN FET transistors face challenges in achieving optimal performance metrics such as Miller ratio, Cgs and Cgd ratio, switching time, and switching energy due to limitations in gate overhang widths, via distribution, and field plate design, which affect reliability and efficiency.
Innovation Solution
A GaN FET design featuring specific dimensions for gate-drain and gate-source overhangs, a widening of the gate metal layer, multiple type 1 vias for fast voltage distribution, a second field plate, and type 2 vias matched to drain and source plate widths to enhance electrical field distribution and current handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate overhang widths are increased to reduce Miller effect, then switching speed improves, but device complexity increases
Solution Approach 1:
The gate metal layer is segmented into multiple distinct components: gate-drain overhang, gate-source overhang, and central gate portion with widening. Each segment serves a specific function in controlling the electric field distribution, allowing independent optimization of switching speed and Miller effect reduction without requiring complete redesign of the entire gate structure.
Solution Approach 2:
Different regions of the gate metal layer are given different widths and configurations tailored to local requirements. The gate-drain overhang is optimized for reducing Miller capacitance, the gate-source overhang for controlling gate-source capacitance, and the central portion with widening for current handling, thereby achieving improved switching speed through localized optimization rather than uniform design.
2Loss of time
If multiple type 1 vias are distributed along longitudinal dimension for fast voltage distribution, then switching time decreases, but manufacturing precision requirements increase
Solution Approach 1:
The voltage distribution function is segmented across multiple type 1 vias distributed along the longitudinal dimension of the transistor cell. Instead of relying on a single via or simple connection, the invention uses several vias (at least three) to create multiple parallel current paths, thereby reducing the overall RC time constant and enabling faster voltage distribution during switching transitions.
Solution Approach 2:
The via distribution is extended from a simple two-point connection to a multi-point distribution along the longitudinal dimension. This dimensional expansion creates a gradient of voltage distribution points that collectively reduce the effective resistance and capacitance in the signal path, achieving faster switching without requiring excessive precision in any single via location.
3Reliability
If second field plate is added to extend metal 1 layer beyond metal 0 layer, then electrical field distribution improves, but device complexity increases
Solution Approach 1:
The metal 1 layer is extended beyond the metal 0 layer to form a second field plate that protrudes toward the center of the transistor cell. This preliminary structural arrangement is designed to pre-establish favorable electric field distribution before the device enters operation, reducing field concentration at critical regions and improving overall reliability without requiring active control during operation.
Solution Approach 2:
The extended metal 1 layer serves multiple functions simultaneously: it acts as a field plate for electric field control, provides additional grounding path, and contributes to overall device stability. This multi-functionality allows the same structural element to improve reliability across multiple performance metrics while minimizing the increase in device complexity.
4Power
If type 2 vias are matched to drain and source plate widths for current handling, then power transmission efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The type 2 vias are strategically positioned and sized to match the local current density requirements at different regions of the drain and source plates. Areas with higher current density receive more or larger vias, while lower density regions have fewer or smaller vias. This localized matching optimizes power transmission efficiency by ensuring adequate current carrying capacity where needed without unnecessarily increasing manufacturing complexity across the entire device.
Data Source
AI summary
A GaN field effect transistor (FET) including a plurality of transistor cells. A gate metal layer of a transistor cell includes a gate-drain overhang (width 0.2 um to 2.5 um) and a gate-source overhang (width 0.3 um to 1 um), and a widening at each narrow edge of the transistor cell, wherein the width of the widening of gate metal layer (150) is of 2-5 um. A metal (1) layer of the transistor sell extends beyond metal (0) layer. A last metal layer includes a drain plate and a source plate, each having a trapezoid form. More than two vias are located at a widening for connecting the gate metal layer to the gate bus. More than six vias distributed along the longitudinal dimension of the transistor cell connect metal (1) layer to metal (0) layer. A plurality of type 2 vias connect metal (1) layer to the last metal layer.