GaN FET Gate Wiring Layout for Low-Resistance High-Power Switching

Solution Overview

Problem

Conventional GaN-FET layouts face increased gate wire resistance and chip size issues due to lengthy gate collective wires, hindering high-speed switching characteristics, especially in high-power applications.

Innovation Solution

The semiconductor device features finger-shaped source and drain electrodes with gate electrodes positioned between them, connected via alternating gate collective wires extending perpendicular to the gate electrode direction, reducing resistance and chip size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the number of unit transistors is increased to increase output, then the output power is improved, but the gate wire length increases leading to increased gate wire resistance

Engineering Contradiction:

Improveoutput powerVSAvoidgate wire resistance

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The gate collective wire is divided into multiple segments (first gate collective wire, second gate collective wires, and third gate collective wire) that are arranged in an alternating pattern with source pads. This segmentation reduces the effective wire length and resistance while maintaining the ability to drive multiple unit transistors for high output power.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gate collective wires extend in a direction perpendicular to the lengthwise direction of the gate electrode, creating a multi-dimensional wiring layout. This dimensional change allows for shorter wire lengths and reduced resistance compared to conventional linear arrangements.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the chip size is increased to accommodate longer gate collective wires, then the gate wire resistance is reduced, but the chip size increases

Engineering Contradiction:

Improvegate wire resistanceVSAvoidchip size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The gate collective wire is divided into multiple segments (first gate collective wire, second gate collective wires, and third gate collective wire) that are arranged in an alternating pattern with source pads. This segmentation reduces the effective wire length and resistance while maintaining the ability to drive multiple unit transistors for high output power.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gate collective wires extend in a direction perpendicular to the lengthwise direction of the gate electrode, creating a multi-dimensional wiring layout. This dimensional change allows for shorter wire lengths and reduced resistance compared to conventional linear arrangements.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If a thin and narrow gate collective wire is used, then the chip size is reduced, but the gate wire resistance increases

Engineering Contradiction:

Improvechip sizeVSAvoidgate wire resistance

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The gate collective wire is divided into multiple segments (first gate collective wire, second gate collective wires, and third gate collective wire) that are arranged in an alternating pattern with source pads. This segmentation reduces the effective wire length and resistance while maintaining the ability to drive multiple unit transistors for high output power.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple gate collective wires (first, second, and third) are combined in parallel to provide low-resistance current paths. This merging of multiple wiring paths reduces the overall resistance while maintaining a compact chip layout.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for reduced gate wire resistance, enabling high-speed switching operations, miniaturization, and improved reliability by minimizing parasitic oscillation and electromigration, while allowing larger gate currents for efficient switching.

Implementation Method 1

two-dimensional electron gas generated by spontaneous polarization and piezo-electric polarization at the heterojunction interface of the channel layer and the barrier layer

Methodology Applied

Scientific EffectSpontaneous polarization: Polarisation

Implementation Method 2

two-dimensional electron gas generated by spontaneous polarization and piezo-electric polarization at the heterojunction interface of the channel layer and the barrier layer

Methodology Applied

Scientific EffectPiezo-electric polarization: Piezoelectric Effect

Data Source

PatentUS12431411B2Semiconductor device and semiconductor component including the same

Publication Date: 2025.09.30 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD

AI summary

A semiconductor device includes: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; finger-shaped source electrodes on the second nitride semiconductor layer; finger-shaped drain electrodes disposed so as to be spaced apart from the source electrodes; and finger-shaped gate electrodes respectively disposed between the source electrodes and the drain electrodes. The gate electrodes are electrically connected, via a first gate integrated wiring, a plurality of second gate integrated wirings and a third gate integrated wiring, to gate pads located on one or both ends of the third gate integrated wiring. A plurality of source pads and the plurality of second gate integrated wirings are formed alternately in a first direction perpendicular to the longitudinal direction of the gate electrodes.