GaN FET Source-Drain Pad Cutouts for Parasitic Capacitance Reduction

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Solution Overview

Problem

Conventional GaN-based FETs suffer from high source-drain parasitic capacitance, leading to issues like ringing, decreased switching speed, and increased switching loss, as well as potential breakdown of low-withstand-voltage Si MOSFETs due to surge voltages in cascode connections.

Innovation Solution

A GaN-based field-effect transistor design featuring source and drain electrode pads with cutouts to reduce parasitic capacitance, where the source electrode pad covers less area over the drain electrodes and vice versa, along with a gate electrode between them, and a cascode connection circuit with a normally-ON GaN FET and a normally-OFF Si MOSFET to control the circuit's on/off state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If a pad-on-element structure is used to achieve device compaction, then the device area is reduced, but the source-drain parasitic capacitance increases

Engineering Contradiction:

Improvedevice areaVSAvoidsource-drain parasitic capacitance

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The electrode pads are segmented with cutouts that correspond to the finger-like electrodes, creating multiple separate contact regions instead of continuous pads. This segmentation reduces the overlapping area between source and drain pads, thereby reducing parasitic capacitance while maintaining compact device area through the distributed finger structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The source electrode pad and drain electrode pad are designed with asymmetric cutout patterns relative to each other. The source pad has cutouts that align with drain fingers, and the drain pad has cutouts that align with source fingers, creating an interdigitated asymmetric pattern that minimizes parasitic capacitance while maintaining electrical connectivity

Inventive Principle:

Principle #4Asymmetry

2Ease of operation

If GaN FET and Si MOSFET are connected in cascode to achieve normally-OFF operation, then the switching control is improved, but surge voltage causes Si MOSFET breakdown

Engineering Contradiction:

Improveswitching controlVSAvoidSi MOSFET breakdown

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent converts the potentially harmful surge voltage effect into a beneficial control mechanism. By carefully designing the cascode connection and utilizing the parasitic capacitance rather than eliminating it completely, the circuit leverages the capacitance to control the voltage transition timing, allowing the Si MOSFET to remain in safe operating conditions while achieving normally-OFF functionality

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The gate electrode structure and insulating layer arrangement act as an intermediary between the GaN FET and Si MOSFET, controlling the voltage distribution and transition at the cascade connecting point. This intermediary structure prevents direct surge voltage transmission to the Si MOSFET while maintaining the cascode switching control benefit

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9306558B2Field-effect transistor

Publication Date: 2016.04.05 ROHM CO LTD

AI summary

This FET includes: a source electrode pad, which is formed on a source electrode and which is electrically connected to the source electrode; and/or a drain electrode pad, which is formed on the drain electrode and which is electrically connected to the drain electrode. The source electrode pad has a cutout for reducing a parasitic capacitance between the source electrode pad and the drain electrode, and the drain electrode pad has a cutout for reducing a parasitic capacitance between the drain electrode pad and the source electrode.