GaN FET with npn Laminated Structure for Threshold Voltage Control
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Solution Overview
Problem
Conventional GaN based field effect transistors face difficulties in controlling the threshold voltage and maintaining low on-resistance, with threshold voltages ranging from 0 V to +1 V, making it challenging to achieve a reliable normally-off operation.
Innovation Solution
A GaN based semiconductor element with a npn laminated structure, including a p-type GaN layer, is designed with a gate electrode and insulating film configuration that allows for the formation of an inversion layer only when a forward voltage greater than or equal to the threshold is applied, enabling control of the threshold voltage by adjusting the thickness and impurity concentration of the p-type GaN layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional GaN based field effect transistor structure is used, then the device can operate with large electronic current and low on-resistance, but the threshold voltage cannot be controlled and ranges from 0 V to +1 V, making it difficult to achieve reliable normally-off operation
Solution Approach 1:
The patent applies parameter changes by introducing a p-type GaN layer with specific thickness (50-500 nm) and impurity concentration (1×10^17 to 1×10^19 atoms/cm³) to control the threshold voltage. By adjusting these parameters, the threshold voltage is increased to a positive value range, enabling reliable normally-off operation while maintaining low on-resistance through optimized layer design
2Reliability
If the threshold voltage is increased to achieve normally-off operation, then the device reliability improves, but the on-resistance may increase, reducing current carrying capability
Solution Approach 1:
The patent applies local quality by creating an npn laminated structure with spatially varying properties: the p-type GaN layer is localized at the sidewall region with specific dimensions and doping characteristics, while the channel region maintains high electron mobility. This localized structuring allows threshold voltage control without significantly degrading the on-resistance, as the inversion layer forms only where needed for voltage control
Solution Approach 2:
The patent transitions from a planar structure to a three-dimensional npn laminated structure with sidewall inversion layer formation. The gate electrode extends along the sidewall region, creating a vertical field effect that induces inversion layers at the sidewalls. This dimensional change allows independent control of threshold voltage through the p-type layer parameters while preserving low on-resistance through the optimized channel structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively achieves a normally-off GaN based field effect transistor with a positive threshold voltage while maintaining low on-resistance, improving voltage resistance and reducing current collapse.
Implementation Method 1
When a forward voltage greater than or equal to the threshold is applied to the gate electrode, an inversion layer is formed to provide a channel at the sidewall portion of the npn laminated structure, so that the drain current flows
Data Source
AI summary
The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.