GaN Vertical Fin FET Layout for Uniform Gate Regrowth
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Solution Overview
Problem
Existing semiconductor manufacturing techniques face challenges in achieving uniform regrowth of gate layers in vertical fin-based FET structures, leading to variations in gate resistivity and channel lengths, which affect the reliability and performance of power semiconductor devices.
Innovation Solution
A semiconductor structure and method involving a fin array with predetermined physical layouts across the substrate, where a plurality of rows and columns of fins are arranged to achieve a uniformly planar epitaxially regrown gate layer, reducing thickness variations and improving channel length consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional epitaxial regrowth methods are used on large arrays of fins, then manufacturing simplicity is maintained, but regrowth uniformity deteriorates leading to thickness variations and channel length variations
Solution Approach 1:
The fin array is divided into multiple rows and columns with specific spacing relationships. By segmenting the array into discrete positional units with controlled dimensions, the patent achieves uniform regrowth across the entire array while maintaining manufacturability through standardized fin configurations.
Solution Approach 2:
The patent applies different fin configurations to different regions of the array. Specifically, fins in different rows and columns have different lengths and spacing to compensate for position-dependent regrowth variations, ensuring uniform gate thickness and channel length across the entire device array.
2Productivity
If fins are arranged in dense arrays to increase device capacity, then productivity is improved, but regrowth uniformity deteriorates due to position-dependent variations
Solution Approach 1:
The patent implements position-dependent fin design where fins at different locations in the array have different dimensions and spacing. This local customization compensates for the position-dependent regrowth variations that occur in dense arrays, enabling uniform gate formation while maintaining high device capacity through increased fin density.
Solution Approach 2:
The patent extends the fin array arrangement into two dimensions (rows and columns) with specific geometric relationships. By controlling the spatial distribution of fins in multiple dimensions, the patent achieves uniform regrowth across the entire array while maximizing device capacity through optimized packing density.
3Manufacturing precision
If non-uniform fin lengths are used to compensate for regrowth variations, then regrowth uniformity is improved, but device structure complexity increases
Solution Approach 1:
The patent applies different fin lengths to different positions in the array based on their specific regrowth characteristics. Fins closer to the array center have different lengths compared to fins at the edges, compensating for position-dependent regrowth variations and achieving uniform channel lengths across the entire device.
Solution Approach 2:
The fin array is pre-configured with specific length variations before the regrowth process. This preliminary design accounts for and compensates for the position-dependent regrowth variations that will occur during manufacturing, ensuring uniform final dimensions without requiring complex real-time adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in improved regrowth uniformity, reduced gate resistivity variation, and enhanced reliability of semiconductor devices by ensuring equal channel lengths across the fin array, thereby improving switch resistance and capacitance.
Implementation Method 1
an epitaxially regrown gate layer... filling the recess region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first conductivity type, a drift layer of the first conductivity type coupled to the semiconductor substrate, a fin array having a first row of fins and a second row of fins on the drift layer, and a space between the first row of fins and the second row of fins. The first row of fins includes a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins includes a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance.