GaN FinFET Power Amplifier Integration with MOS Control Logic
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Solution Overview
Problem
Conventional two-dimensional GaN-based power amplifiers for 5G and mmW applications face challenges with high thermal effects and limited thermal dissipation, while three-dimensional GaN-based power amplifiers lack in-chip control logic, leading to inefficiencies.
Innovation Solution
A semiconductor device structure integrating a vertical fin field-effect transistor (FinFET) power amplifier with a horizontal metal-oxide-semiconductor (MOS) control logic device on the same wafer-level substrate, enabling efficient thermal dissipation and in-chip control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional two-dimensional GaN-based power amplifiers are used, then the device can be manufactured with standard planar processes, but thermal dissipation is limited and thermal effects are high
Solution Approach 1:
The patent transitions from conventional two-dimensional planar transistor structures to a three-dimensional vertical FinFET architecture. This dimensional change enables current to flow through the entire wafer thickness, dramatically improving thermal dissipation by utilizing the vertical dimension for heat extraction pathways while maintaining compatibility with standard semiconductor manufacturing processes through adapted fin formation and doping techniques.
2Temperature
If three-dimensional GaN-based power amplifiers are used, then thermal dissipation is improved, but in-chip control logic is lacking
Solution Approach 1:
The patent merges previously separate components (vertical FinFET power amplifier and horizontal MOS control logic) into a single integrated device structure. The control logic section is fabricated adjacent to the FinFET region on the same wafer, enabling in-chip control of the power amplifier while preserving the superior thermal characteristics of the vertical architecture. This integration is achieved through coordinated processing steps that form both the vertical fins and horizontal control transistors in the same semiconductor substrate.
3Temperature
If vertical FinFET structure is used for power amplifier, then thermal dissipation is enhanced through wafer-level current flow, but device structure complexity increases
Solution Approach 1:
The patent segments the semiconductor device into distinct functional regions: a vertical FinFET region for power amplification and a horizontal MOS region for control logic. This segmentation allows each region to be optimized for its specific function while sharing common processing steps. The FinFET structure is formed by creating vertical fins in the substrate, followed by selective doping and gate formation, while the control logic region uses conventional planar transistor fabrication, thereby managing structural complexity through functional separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration enhances thermal dissipation and power efficiency by allowing current flow through the entire wafer, reducing heat concentration and improving control over the power amplifier parameters.
Implementation Method 1
at least one first path is formed between the at least one first drain contact and the at least one first source contact for a first current flow through the at least one first fin in a vertical direction along the at least one first path
Implementation Method 2
The horizontal MOS device is configured to control at least one parameter of the vertical FinFET device
Data Source
AI summary
Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a semiconductor region disposed adjacent to the substrate, first fin(s) disposed adjacent to the semiconductor region, first gate region(s) disposed adjacent to the first fin(s), first drain contact(s) disposed above the first fin(s), first source contact(s) disposed below the substrate, a second fin disposed above the semiconductor region, and a second gate region, second source contact and second drain contact disposed adjacent to the second fin and above the semiconductor region. First path(s) are formed between the first drain contact(s) and the first source contact(s) for current flow(s) through the first fin(s) in a vertical direction along the first path(s). A second path is formed between the second source contact and the second drain contact for current flow through the second fin in a horizontal direction along the second path.