GaN Flip Chip Package Interdigitated Leadframe Creepage

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Solution Overview

Problem

GaN-based semiconductor devices require electronic packages that can accommodate closely spaced interdigitated source and drain connections while meeting high voltage creepage and clearance requirements, and existing packages struggle to provide the necessary support and protection for these devices during manufacturing and environmental exposure.

Innovation Solution

The development of electronic packages with leadframes that have interdigitated terminal fingers, where the internal connections are closely spaced to support high voltage operations, and the use of encapsulants and dielectric layers to ensure electrical continuity and environmental protection, along with the removal of bottom leadframe portions to create channels for increased creepage and clearance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the internal spacing between source and drain connections is reduced to accommodate closely spaced interdigitated connections, then the device can achieve better performance and smaller size, but the external spacing between package interconnects becomes insufficient to meet high voltage creepage and clearance requirements

Engineering Contradiction:
Improvedevice sizeVSAvoidcreepage and clearance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent resolves the spacing contradiction by transitioning from a two-dimensional planar layout to a three-dimensional structure. Channels are formed extending vertically through the leadframe from the top surface to the bottom surface, creating additional spatial dimension for voltage isolation. This allows closely spaced interdigitated source and drain connections on the device level while maintaining adequate creepage and clearance distances through the vertical channel structure at the package level.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The leadframe is segmented into multiple functional regions: terminal fingers for electrical connection, channels for voltage isolation, and retention structures for mechanical support. The channels are selectively formed between specific terminal fingers (e.g., between first and second terminal fingers, and between third and fourth terminal fingers) to provide targeted creepage and clearance paths. This segmentation allows different parts of the package to serve different functions - tight spacing where needed for performance and adequate spacing where needed for safety.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If retention structures are added to support closely spaced terminal fingers during manufacturing, then structural support and alignment are improved, but additional manufacturing steps and process complexity are required

Engineering Contradiction:
Improvealignment precisionVSAvoidmanufacturing process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Retention structures are incorporated into the leadframe design before the semiconductor device is mounted. These retention structures protrude from the bottom surface of the leadframe and engage with corresponding features on the device package to pre-establish precise alignment and mechanical support. This preliminary positioning action simplifies subsequent assembly steps by ensuring correct placement before final encapsulation, rather than requiring complex alignment procedures during device mounting.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The retention structures are merged with the leadframe as an integrated component rather than being separate auxiliary elements. The leadframe simultaneously provides electrical connection through terminal fingers, mechanical support through retention structures, and voltage isolation through channels. This merging of multiple functions into a single integrated component reduces the total number of parts and assembly steps, offsetting the initial complexity of forming the retention structures.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If channels are formed in the leadframe to increase creepage and clearance, then electrical isolation and safety are improved, but the leadframe structure becomes more complex and manufacturing难度 increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidmanufacturing difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The formation of channels in the leadframe replaces complex mechanical drilling or machining operations with a chemical etching process. The leadframe material (typically copper or copper alloy) is selectively removed using chemical etchants that can precisely define channel geometry and depth. This substitution of chemical for mechanical processes enables more accurate and consistent channel formation, particularly for the vertical through-channels required for high voltage isolation, while simplifying the manufacturing equipment requirements.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

Channels are not formed uniformly throughout the entire leadframe but are selectively created only in specific locations where voltage isolation is required. The channels are positioned between specific terminal fingers (e.g., between first and second terminal fingers, and between third and fourth terminal fingers) to provide targeted creepage and clearance paths. This localized approach minimizes the amount of material removed and reduces manufacturing complexity compared to forming channels throughout the entire structure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10269687B2Electronic packages for flip chip devices
Publication Date: 2019.04.23 NAVITAS SEMICON LTD
  • US10269687B2 patent drawing
  • US10269687B2 patent drawing
  • US10269687B2 patent drawing

AI summary

Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a GaN-based semiconductor device, and are encased in an encapsulant. The plurality of leads are interdigitated and are at different voltage potentials.