GaN Transistor Front Barrier Structure for 2DEG and Threshold Control

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Solution Overview

Problem

GaN transistors face challenges in simultaneously minimizing gate leakage and achieving high electron density in the channel, as traditional single-layer passivation insulators cannot achieve both simultaneously, and there is a need to adjust threshold voltages for both enhancement and depletion mode devices in a single integrated circuit.

Innovation Solution

A multi-thickness front barrier layer with progressively increasing thickness between the gate and drain, formed of alternating AlGaN and GaN layers or a single AlGaN layer, etched to varying thicknesses, which induces a laterally varying 2DEG density, allowing customization of threshold voltage and enabling both enhancement and depletion mode operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If a single-layer passivation insulator is used, then gate leakage is minimized, but electron density in the channel cannot be sufficiently increased

Engineering Contradiction:
Improvegate leakageVSAvoidelectron density in channel
Core Design Contradiction:
Object-generated harmful factorsVSQuantity of substance

Solution Approach 1:

The passivation insulator is divided into multiple discrete layers (first passivation layer and second passivation layer) with different dielectric constants. The first layer has higher dielectric constant and the second layer has lower dielectric constant, allowing each layer to contribute differently to the electrical characteristics and achieve both low gate leakage and high channel electron density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the insulator structure have different dielectric properties. The first passivation layer positioned closer to the gate utilizes high dielectric constant material to suppress gate leakage, while the second passivation layer utilizes lower dielectric constant material to optimize channel electron density, creating localized functional zones within the insulator structure

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If threshold voltage is adjusted for enhancement mode devices, then device performance is optimized, but depletion mode devices with negative threshold voltages cannot be achieved in the same integrated circuit

Engineering Contradiction:
Improvethreshold voltage rangeVSAvoidintegrated circuit configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The multi-layer passivation insulator structure serves multiple functions simultaneously: it enables both enhancement mode and depletion mode device operation within the same integrated circuit by providing adjustable electrical characteristics that can accommodate different threshold voltage requirements through the combination of layers with different dielectric constants

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively reduces gate leakage, increases electron density near the drain, and allows for customizable threshold voltages, enabling the production of transistors with varying threshold voltages, including depletion mode transistors with negative threshold voltages, in a single integrated circuit.

Implementation Method 1

The different crystallinity in the adjacent nitride layers also causes polarization, which contributes to a conductive two-dimensional electron gas (2DEG) region near the junction of the two layers

Methodology Applied
Scientific EffectPolarization: Polarisation

Data Source

PatentUS20240413205A1GaN TRANSISTOR HAVING MULTI-THICKNESS FRONT BARRIER
Publication Date: 2024.12.12 EFFICIENT POWER CONVERSION CORP
  • US20240413205A1 patent drawing
  • US20240413205A1 patent drawing
  • US20240413205A1 patent drawing

AI summary

A gallium nitride (GaN) transistor which includes a multi-layer/multi-thickness barrier layer formed of segments of progressively increasing thickness between the gate and drain to progressively increase the 2DEG density in the channel from gate to drain. The GaN gate can be formed on the base barrier layer to produce an enhancement mode device with a positive threshold voltage. By forming the gate over a thicker segment of the barrier layer, a GaN transistor with a less positive threshold voltage, or a depletion mode transistor with a negative threshold voltage, can be produced.