Four-Phase GaN Gate Buffer Circuit for Rail-to-Rail Switching
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Solution Overview
Problem
Conventional GaN driver circuits face limitations such as lack of complementary p-channel transistors, leading to increased static power consumption and circuit complexity, especially in high-speed digital applications, and inefficiencies in implementing push-pull stages and comparators with limited voltage ranges.
Innovation Solution
A fully integrated GaN driver circuit implemented in monolithic GaN technology, featuring a buffer circuit with a push-pull stage and pre-buffer sections, enabling rail-to-rail driving and reduced power consumption, using enhancement-mode transistors and depletion-mode transistors to control gate signals in four phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GaN driver circuits are used, then the circuit can be implemented, but static power consumption increases and circuit complexity increases due to lack of complementary p-channel transistors
Solution Approach 1:
The push-pull stage is segmented into four distinct enhancement-mode transistors (first, second, third, and fourth transistors) that operate in four consecutive phases, replacing the conventional single-stage design. This segmentation allows each transistor to be independently controlled, enabling complete rail-to-rail voltage swing while maintaining low static power consumption through the complementary action of n-channel and p-channel enhancement-mode devices.
Solution Approach 2:
The invention changes the operational parameters of the transistors by utilizing enhancement-mode devices with complementary characteristics. The first and second transistors (n-channel enhancement-mode) and third and fourth transistors (p-channel enhancement-mode) are configured to operate in alternating phases, changing the voltage and conduction state parameters dynamically to achieve both low static power consumption and complete voltage swing capability.
2Reliability
If conventional GaN driver circuits are used, then the circuit can be implemented, but circuit complexity increases due to lack of complementary p-channel transistors
Solution Approach 1:
The push-pull stage is segmented into four distinct enhancement-mode transistors (first, second, third, and fourth transistors) that operate in four consecutive phases, replacing the conventional single-stage design. This segmentation allows each transistor to be independently controlled, enabling complete rail-to-rail voltage swing while maintaining low static power consumption through the complementary action of n-channel and p-channel enhancement-mode devices.
Solution Approach 2:
The invention changes the operational parameters of the transistors by utilizing enhancement-mode devices with complementary characteristics. The first and second transistors (n-channel enhancement-mode) and third and fourth transistors (p-channel enhancement-mode) are configured to operate in alternating phases, changing the voltage and conduction state parameters dynamically to achieve both low static power consumption and complete voltage swing capability.
3Speed
If monolithic GaN technology is used, then parasitic inductance is reduced and switching speed is improved, but manufacturing complexity increases
Solution Approach 1:
The driver circuit and power switches are merged into a single monolithic GaN device, integrating the push-pull stage with complementary enhancement-mode transistors directly on the GaN substrate. This merging eliminates external interconnections, reducing parasitic inductance and improving switching speed, while the standardized four-transistor architecture simplifies the manufacturing process compared to hybrid approaches.
Solution Approach 2:
The invention utilizes composite GaN material structure with both n-channel and p-channel enhancement-mode transistors fabricated on the same substrate. This composite transistor architecture enables complementary push-pull operation while leveraging the superior material properties of GaN for high-frequency, low-loss operation, and the integrated fabrication process reduces manufacturing complexity.
Data Source
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AI summary
A buffer circuit (224, 226) for driving a GaN power switch (QPE) includes an input node (300) to receive an input signal (in) and an output node (302) to produce a gate signal (gate) for the GaN power switch. The buffer includes a push-pull stage that includes a first transistor (QE1) coupled between a supply voltage node (V+) and the output node(302), a second transistor (QE2) coupled between the supply voltage node (V+) and the output node(302), a third transistor (QE3) coupled between the output node(302) and a reference voltage node (V-), and a fourth transistor (QE4) coupled between the output node(302) and the reference voltage node (V-). The buffer includes a pre-buffer stage configured to receive the input signal (in) and to produce respective driving signals for the first (QE1), second (QE2), third (QE3) and fourth (QE4) transistors to produce the gate signal (gate) at the output node (302) in four consecutive phases. In a first phase, the first transistor (QE1) is conductive, and the second (QE2), third (QE3) and fourth (QE4) transistors are not conductive. In a second phase, the first (QE1) and second (QE2) transistors are conductive, and the third (QE3) and fourth (QE4) transistors are not conductive. In a third phase, the third transistor (QE3) is conductive, and the first (QE1), second (QE2) and fourth (QE4) transistors are not conductive. In a fourth phase, the third (QE3) and fourth (QE4) transistors are conductive, and the first (QE1) and second (QE2) transistors are not conductive.