P-Type GaN Epitaxial Gate Structure for Thick Buffer Uniformity
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Solution Overview
Problem
Existing gallium nitride field effect transistors (GaN FETs) face challenges in achieving uniform gate thickness and efficient operation above several hundred volts due to the complexity of the buffer layer structure and the need for precise control of epitaxial growth processes.
Innovation Solution
The semiconductor device incorporates a buffer layer with a columnar region, a transition region, and an inter-columnar region, along with a gate layer that has a specific thickness and aluminum content variation across these regions, optimized through MOVPE processes to enhance uniformity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick buffer layer is used to isolate the GaN FET from the silicon substrate for high-voltage operation, then the electrical isolation and breakdown voltage are improved, but the vertical surface profile variation increases making uniform gate thickness difficult to achieve
Solution Approach 1:
The patent applies local quality by creating distinct regions within the buffer layer with different properties: a columnar region with controlled vertical profile for uniform gate formation, and an inter-columnar region that accommodates the natural surface variation. The gate structure is also designed with different thicknesses in different regions to match the underlying buffer profile, ensuring uniform electrical characteristics despite topographical variations.
Solution Approach 2:
The patent resolves the surface profile problem by transitioning from a two-dimensional uniform thickness requirement to a three-dimensional solution where the gate thickness varies laterally across different buffer regions. The gate is designed with a first thickness over the columnar region and a second thickness over the inter-columnar region, converting the uniformity problem into a controlled dimensional variation that maintains electrical performance.
2Ease of manufacture
If the buffer layer structure is simplified to ease manufacturing, then the fabrication complexity is reduced, but the ability to achieve high-voltage operation above 500 volts is compromised
Solution Approach 1:
The patent segments the buffer layer into functionally distinct regions: a columnar region providing a controlled growth surface for uniform gate formation, and an inter-columnar region that manages stress and dislocation. This segmentation allows each region to be optimized for its specific function while maintaining overall structural integrity for high-voltage operation.
Solution Approach 2:
The patent utilizes parameter changes in the epitaxial growth process to create the multi-region buffer structure. By controlling growth conditions such as temperature, pressure, and gas flow during MOVPE, the process transitions between forming columnar and inter-columnar regions, enabling complex functionality through controlled parameter variations rather than additional manufacturing steps.
3Manufacturing precision
If precise control of epitaxial growth parameters is maintained to achieve uniform gate thickness, then the manufacturing precision is improved, but the process complexity and difficulty of fabrication increase
Solution Approach 1:
The patent applies preliminary action by pre-structuring the buffer layer with columnar and inter-columnar regions before gate formation. This pre-configuration of the substrate surface eliminates the need for complex real-time adjustments during gate epitaxial growth, as the uniform gate thickness is achieved by designing the underlying buffer structure to provide a controlled growth template.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables improved uniformity in gate thickness and reduced vertical range variations, leading to more consistent electrical performance and increased reliability of GaN FETs for high-voltage applications.
Implementation Method 1
forming the barrier layer over the top surface by a barrier MOVPE process. A gate layer is formed of III-N semiconductor material over the barrier layer by a gate MOVPE process
Data Source
AI summary
A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.