GaN Gate Contacts with Low-k Passivation and Copper Damascene
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Solution Overview
Problem
The fabrication of Group III-Nitride semiconductor devices, particularly GaN HEMTs, faces challenges in achieving low capacitance and resistance gate structures with reliable metal-to-semiconductor contacts, due to defects from lift-off processes and the need for gold-free processing in Si CMOS foundries, which complicates passivation and interconnect formation.
Innovation Solution
A semiconductor structure is designed with a gold-free gate electrode contact structure comprising a T-shaped stem and a horizontal portion with a low dielectric constant passivation layer, and copper Damascene interconnects, using silicon nitride and copper to minimize capacitance and resistance, and prevent contamination, while maintaining high yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lift-off process is used to define metal lines, then metal-to-semiconductor contacts can be formed, but defects such as residue and ragged edges occur reducing manufacturing precision
Solution Approach 1:
The patent inverts the traditional lift-off approach by using a subtractive process where metal is deposited first and then selectively removed. Instead of depositing metal only where needed (lift-off), the metal is deposited over the entire surface and then etched back to expose the semiconductor, achieving cleaner edges and better contact interfaces without the residue and fencing problems of lift-off processes
Solution Approach 2:
The patent replaces the mechanical lift-off process with a chemical etching process. Instead of using solvent to remove mask and metal (mechanical/lift-off), the patent uses selective etchants to remove metal in a controlled manner, achieving superior edge acuity and contact quality through chemical means rather than mechanical removal
2Reliability
If gold is used to reduce sheet resistance and oxidation, then contact resistance decreases, but gold-free processing is required in Si CMOS foundries
Solution Approach 1:
The patent changes the material parameter from gold to alternative metals such as copper or aluminum that are compatible with Si CMOS foundries. By adjusting the metal stack composition and deposition parameters, the patent achieves low contact resistance without requiring gold, enabling fabrication in standard CMOS foundries while maintaining electrical performance
Solution Approach 2:
The patent uses composite metal stacks combining multiple materials (e.g., copper with barrier layers, or aluminum with adhesion layers) to achieve the benefits of gold (low resistance, oxidation resistance) without using gold itself. These composite structures provide both electrical performance and foundry compatibility through carefully selected material combinations
3Object-affected harmful factors
If traditional passivation layers are used, then contamination is prevented, but capacitance increases reducing high-frequency performance
Solution Approach 1:
The patent applies different dielectric materials with different properties to different regions. The gate dielectric has low-k characteristics to minimize capacitance and improve high-frequency performance, while the field dielectric provides contamination protection and mechanical support. This local differentiation of material properties achieves both low capacitance and effective passivation
Solution Approach 2:
The patent segments the passivation structure into distinct functional layers: a gate dielectric layer specifically for minimizing gate capacitance and a field dielectric layer for contamination protection and mechanical support. This segmentation allows each layer to be optimized for its specific function, achieving both low capacitance and effective passivation simultaneously
4Adaptability or versatility
If subtractive processing is used to achieve gold-free fabrication, then foundry compatibility improves, but process complexity increases
Solution Approach 1:
The patent uses universal subtractive processing techniques (deposition, patterning, etching, CMP) that are already standard in Si CMOS foundries. By making the process multi-functional and compatible with existing foundry equipment and methodologies, the patent achieves foundry compatibility without significantly increasing process complexity, as the same toolset performs multiple functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces gate capacitance and resistance, enhances high-frequency performance, and ensures reliable passivation and contamination control, addressing the limitations of lift-off processes and gold-free processing requirements in Si CMOS foundries.
Implementation Method 1
first dielectric having a higher dielectric constant than the second dielectric
Implementation Method 2
copper Damascene based interconnects
Implementation Method 3
silicon nitride and copper to minimize capacitance and resistance, and prevent contamination
Data Source
AI summary
A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.