GaN FET Gate Bias Circuit With Adaptive Current Limiting
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Solution Overview
Problem
Conventional methods for limiting gate current in GaN HEMTs are inadequate, leading to increased forward current and reduced transistor robustness at high input powers, with existing solutions only reducing but not fully controlling the gate current.
Innovation Solution
A circuit arrangement using a first FET and a DC supply network with a high-impedance resistor and a second FET in series, where the second FET blocks in depletion mode based on the gate current, effectively limiting the forward current through a current-dependent adaptive resistance control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a high-impedance resistor is used at the gate to limit gate current, then the transistor can tolerate higher power levels, but the voltage drop across the resistor causes the operating point to shift to low class C operation with increased negative gate voltages
Solution Approach 1:
The patent implements a feedback mechanism where the gate voltage is monitored and used to control a variable impedance element (such as a voltage-controlled resistor or transistor). When gate current increases, the feedback loop adjusts the impedance to maintain the operating point, preventing the shift to class C operation while still limiting the gate current effectively.
Solution Approach 2:
The patent uses a dynamic impedance element that can change its resistance or reactance based on the operating conditions. This dynamic adjustment allows the circuit to provide high impedance for gate current limiting when needed, while maintaining low impedance for signal operation, thus avoiding the fixed operating point shift caused by static high-impedance resistors.
2Reliability
If the gate current is reduced by a high-impedance resistor in the gate supply network, then the transistor is protected from high gate currents, but the forward current at the gate continues to increase with increasing input powers
Solution Approach 1:
The feedback mechanism detects the increase in forward gate current and dynamically adjusts the gate impedance to counteract the current increase. This active control ensures that the gate current remains limited even as input power increases, providing both protection and effective current control.
Solution Approach 2:
The circuit uses the gate current itself to control the limiting mechanism. The increasing forward current automatically triggers a response that increases the gate impedance, creating a self-regulating system that limits current without external intervention while maintaining protection.
3Reliability
If conventional limiter diodes are used at the input, then the gate current can be limited, but the components cannot be monolithically integrated and require a second chip
Solution Approach 1:
The patent uses the FET's own gate structure and associated circuitry to perform both the amplification function and the gate current limiting function. By making the gate impedance controllable and responsive, the same component serves dual purposes, eliminating the need for separate limiter diodes and enabling monolithic integration.
Solution Approach 2:
The patent combines the limiting function with the FET gate structure itself. The variable impedance element is integrated into the gate supply network, merging the protection function with the signal processing function in a single monolithic device, thereby reducing component count and simplifying integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a 20-fold reduction in gate current at high input powers, maintaining small-signal behavior and noise figure, while allowing faster recovery from overload scenarios and enabling monolithic integration for compact, robust LNAs.
Implementation Method 1
the second FET having an ON state at of a gate source voltage of 0 V and having its gate terminal connected to the gate terminal of the first FET via a second connection in parallel with the resistor R1 also; wherein a voltage drop occurring at the resistor R1 results in an increasing blocking of the second FET
Data Source
AI summary
A circuit arrangement for limiting the gate current at a field effect transistor, FET, comprises a first FET and a DC supply network connected to a gate terminal of the first FET; wherein the supply network provides a voltage Vgg to the gate terminal of the first FET via a first connection comprising a high impedance resistor R1 and a second FET connected in series therewith and having a gate terminal; the second FET having an ON state at a gate-source voltage of 0 V and having its gate terminal also connected to the gate terminal of the first FET via a second connection in parallel with the resistor R1; wherein a voltage drop occurring across the resistor R1 results in increasing blocking of the second FET.