Paralleled GaN Gate Drive Layout for Synchronized Turn-Off
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Solution Overview
Problem
In paralleled semiconductor switch arrangements, differences in gate loop inductance cause switches to turn on and off at different speeds, leading to oscillations and potential mis-triggering, which can result in undesired operation or damage, especially in fast switching applications like those using GaN HEMTs.
Innovation Solution
The solution involves distinguishing the gate drive loop for each switch by varying the length of the electrical connections and adding impedance elements like resistors or capacitors to delay the turn-off time of switches with lower loop inductance, ensuring they turn off after those with higher loop inductance, thereby reducing oscillations and promoting zero voltage turn-off switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If identical gate drive circuits are used for all switches in parallel arrangement, then device complexity is reduced, but oscillation and mis-triggering occur due to differences in gate loop inductance
Solution Approach 1:
The patent applies local quality by assigning different gate loop configurations to different switches based on their physical position. Specifically, the near switch (closer to the gate drive chip) has a shorter gate loop with smaller inductance, while the far switch (farther from the gate drive chip) has a longer gate loop with larger inductance. This localized differentiation compensates for the inherent inductance differences caused by physical layout, ensuring that both switches turn off simultaneously and preventing oscillation and mis-triggering.
2Reliability
If the electrical connection length is increased to balance turn-off timing, then switch synchronization is improved, but gate loop inductance increases causing slower switching speed
Solution Approach 1:
The patent applies parameter changes by carefully selecting and adjusting the gate loop parameters (length, inductance) for each switch. The far switch uses a longer electrical connection to increase its gate loop inductance, which slows down its turn-off timing to match the near switch. This parameter adjustment achieves turn-off synchronization while managing the trade-off with switching speed by optimizing the inductance values to be just sufficient for synchronization without excessive delay.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces oscillations and mis-triggering, improving the reliability and efficiency of the paralleled switch operation by ensuring synchronized turn-off of switches, thus minimizing system noise and preventing damage.
Implementation Method 1
the first electrical connection has first length and comprises electrically conductive material with an associated first inductance. The second electrical connection has a second length and comprises electrically conductive material with an associated second inductance.
Implementation Method 2
adding impedance elements like resistors or capacitors to delay the turn-off time of switches with lower loop inductance
Data Source
Figure 1A~1B
Figure 2A~2D
Figure 3
AI summary
A driver circuit has a gate drive terminal that produces a gate drive signal to control paralleled power semiconductor switches, such as GaN high electron mobility transistor (HEMT) devices. One of the switches is closest to the gate drive terminal such that its gate drive loop inductance is smaller than the remaining switches that are farther away having a larger loop inductance. An additional resistor or gate-source capacitor is provided in the gate drive circuit of the closest switch which increases the total gate resistance of the closest switch compared to the remaining switches, which delays the turn off time of the closest switch. The delay permits zero voltage switching turn-off of the remaining switches to reduce noise. The closest switch is hard switched off but has the smallest loop inductance, which allows optimized turn off.