GaN Gate Driver Bootstrapping for Fast Pull-Up and Low Quiescent Power
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Solution Overview
Problem
GaN-based P-channel FETs are not commercially viable, leading to high quiescent power dissipation and asymmetrical pull-up and pull-down slew rates in modern electronic circuits, which limits their application in analog, digital, RF, and power electronics.
Innovation Solution
A GaN-based inverting logic gate or FET gate driver using a bootstrapping enhancement mode FET in parallel with a traditional pull-up element, driven by the complement of the input signal or the output signal feedback, to enhance pull-up slew rate while maintaining low quiescent power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional pull-up element (resistor or depletion-mode FET) is used in GaN circuits, then the circuit can operate with available components, but the pull-up slew rate becomes slower than the pull-down slew rate due to impedance mismatch
Solution Approach 1:
An enhancement-mode GaN FET is introduced as an intermediary active pull-up element between the power supply and the output node. This mediator provides low-impedance current sourcing capability during the pull-up phase, matching the pull-down slew rate performance while maintaining compatibility with existing GaN process technologies.
Solution Approach 2:
The invention changes the operational parameters of the pull-up path by using an enhancement-mode FET that can be dynamically controlled. By adjusting the gate voltage of the enhancement-mode FET, the pull-up impedance can be optimized to achieve symmetric slew rates with the pull-down path, transforming the static impedance limitation into a dynamic controllable parameter.
2Use of energy by stationary object
If the pull-up element impedance is increased to reduce quiescent power dissipation, then power consumption decreases, but the pull-up slew rate becomes slower relative to the pull-down slew rate
Solution Approach 1:
The invention transforms the static pull-up element into a dynamic controllable device. The enhancement-mode FET's impedance can be dynamically adjusted by controlling its gate voltage, allowing low impedance during switching transitions for fast slew rate and high impedance during steady states for low quiescent power dissipation.
Solution Approach 2:
The enhancement-mode pull-up FET operates in a periodic manner, being activated only during the necessary transition periods to charge the output capacitance, and remaining inactive during steady states. This periodic activation achieves fast slew rates when needed while minimizing quiescent power consumption during stable operation.
3Speed
If enhancement-mode FETs are used for both pull-up and pull-down functions, then symmetric slew rates can be achieved, but the circuit complexity increases due to additional control requirements
Solution Approach 1:
The enhancement-mode FET serves multiple functions: it acts as the active pull-up element for fast charging, provides high-impedance off-state for low power consumption, and can be controlled by simple logic signals. This multi-functionality achieves symmetric slew rates without requiring complex additional circuitry beyond standard logic control.
Data Source
AI summary
A new inverting logic gate or a FET gate driver is disclosed. The logic gate mitigates the trade-off between power dissipation (or quiescent power) and slew rate of the typical RTL and DLL buffers by using an innovative circuit topology involving a pull-up bootstrapping transistor. The bootstrapping transistor may be an enhancement mode GaN field effect transistor (FET). This bootstrapping transistor may be driven by the complement of the input signal. Alternatively, the bootstrapping transistor may monitor the drain terminal of the pull-down transistor and conduct current accordingly. Other Boolean functions may also be achieved using this approach.