GaN Transistor Gate Layout After Ohmic Contact Planarization
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Solution Overview
Problem
Current Group III nitride-based transistors face challenges in achieving short gate lengths and optimized feedback capacitance for high-frequency radio-frequency applications, with existing processing methods being sensitive to topography steps created by ohmic metal contacts, which impairs photolithography accuracy and critical dimension control.
Innovation Solution
An ohmic contact-first approach is used, involving planarization of the ohmic metal before gate structure fabrication, allowing for precise patterning of the gate and field plate using photolithography without underlying topography affecting the process, enabling short gate lengths and improved critical dimension control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used directly on ohmic metal contacts, then the process is simple, but the topography steps created by ohmic metal contacts impair photolithography accuracy and critical dimension control
Solution Approach 1:
The patent applies planarization (chemical mechanical polishing or etch-back) to the ohmic metal contacts before performing photolithography. This preliminary action removes the topography steps created by the ohmic metal contacts, creating a flat surface that enables accurate photolithography patterning and critical dimension control without requiring complex workarounds during the lithography process.
2Speed
If gate length is reduced for high-frequency applications, then transition frequency increases, but achieving short gate lengths becomes more difficult with existing processing methods
Solution Approach 1:
The patent performs planarization of the substrate surface before depositing and patterning the gate electrode. This creates a flat foundation that enables precise photolithography patterning of short gate lengths (e.g., 250 nm or less), allowing the fabrication of high-frequency devices with accurately controlled dimensions that would be difficult to achieve on non-planar surfaces.
3Reliability
If feedback capacitance is optimized for high-frequency performance, then device performance improves, but the processing complexity increases
Solution Approach 1:
The patent applies planarization to create a flat surface before forming the gate and field plate structures. This enables precise control of the spacing and dimensions of these components, which is critical for optimizing feedback capacitance in high-frequency applications. The improved dimensional control allows for better optimization of electrical performance without requiring excessively complex processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the fabrication of Group III nitride-based transistors with reduced gate-to-source distance, enhanced device performance, and improved manufacturability by accurately controlling gate and field plate dimensions, thus achieving high transition frequencies and low resistance.
Implementation Method 1
the first insulating layer and the first photoresist are patterned using DUV (deep ultra violet) technology
Implementation Method 2
depositing an electrically conductive layer into the first via and the second via... the electrically conductive layer is a tungsten layer
Data Source
AI summary
In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.